Introduction to SynqNet
Overview
Features
Physical Layer
Glossary
System Requirements


Topology
SynqNet Topologies (string/ring)
Node, Cable, Motor, Drive Addressing
Save/Clear Topology to Flash

LEDs
Controller (SynqNet and CAN) LEDs
Node LEDs
    - Overview
    - Details
How to use LEDs to find Cable Problems

SynqNet Cables
SynqNet Cable Requirements
SynqNet Custom Cable Guidelines

Node Specific Features
SynqNet Drive Parameters

SynqNet Configuration
System Requirements
Sample Rate
Valid Network Sample Rates
SynqNet Timing Values
Controller Performance
Drive Update Frequency and Period
SynqNet Performance Compatibility
Node Control Latency
Confirming SynqNet Control Latency
Cable Length Discovery Uncertainty Factor
SynqNet Packet Formats
User Configurable Packets
SynqNet Demand Modes   

Configuration Management
Introduction
Version Control
Compatibility
Automated Software Configuration
MPI/SynqNet FPGA Compatibility Check
FAQs

>> For additional information, visit www.synqnet.org

Network Initialization and Verification
Overview of SynqNet Network Initialization
SynqNet Discovery
SynqNet Topology Test
Default Initialization Routine
Automatic Initialization Routine
Save/Clear Topology to Flash
Node Identification (device, vendor, serial number, etc)
Application Verification (responsibilities)
SynqNet Cable Length

Fault Detection and Recovery
SynqNet Network/Node Faults Diagram
    Network States/Status
    Node Status
    SynqNet Fault Recovery
    Packet Error Counters
    Packet Error Rate Counters
    CRC Error Counters
    Node Failure
    IO Abort
    Node Alarm

SynqNet HotReplace   
SynqNet HotReplace

Pulse for Stepper Motors
Introduction
Restrictions
Specifications
Step/Dir and CW/CCW Logic
Configuration

FPGA Images
Overview of Controller FPGA Images
Overview of Node FPGA Images
Drive FPGA Images
Controller FPGA Images Table
Node FPGA Images: Identification Table
Node FPGA Images: Features Table (runtime)