There are up to 32 general purpose I/O signals associated with each drive/motor on a SynqNet node. However, many nodes do not support all 32 I/O signals. These I/O signals can either be an input, output or are sometimes software configurable as either an input/output.
Signals that can be outputs can either be controlled by the user, or the node may allow the output to be a motion specific function, such as a stepper output signal.
For example, Motor 1 on an RMB-10V2 node from MEI (using the C0FE0029 FPGA) supports the following general purpose I/O bits.
15 & 49
16 & 50
17 & 51
Each of the general purpose I/O signals supported by a node has a structure similar to the following diagram.
The I/O signal can either be directly controlled from the output register or monitored with the input register. There are a maximum of 15 other sources that could drive an output pin, although most node types do not have this many internal sources available. The internal feature of the node that could drive each of these sources is dependant upon the node's design and loaded SynqNet FPGA version.
Getting Information about General Purpose I/O
The MPIMotorInfostructure returned from a call to the mpiMotorInfo(...) function returns data about what general purpose I/O is supported and which configuration options are valid for each general purpose I/O signal.
The name field gives the name of the node used for this I/O pin.
The validTypes field returns a bitmap where each true bit indicates that the source type is valid for this motor/node. The following enumerations can be used to decode the validTypes field.
These functions take two arguments, bitStart and bitCount, which allow either a single bit to be accessed (bitCount equals one) or multiple adjacent I/O bits to be accessed (bitCount greater than one).
The following code shows how to get the state of general purpose input 0.
mpiMotorGeneralIn( motor0, 0, 1, &x );
The next piece of code shows how to get the state of all the general purpose outputs:
mpiMotorGeneralOutGet( motor0, 0, MPIMotorGeneralIoLAST, &x );
FPGA I/O Bitmapping
Each SynqNet drive supports different FPGA I/O Bitmapping. Please select a drive from the menu below to see the supported general purpose I/O bits for that particular drive. If the SynqNet drive you are using is not listed, refer to our SynqNet Drives page for more information.