Important Things to Know

Release Type
MPI Version
Release Date
Production Release


This release contains several new features since the 03.02.xx series:


For information about MEI's software life cycle policy and release types, see the Software Life Cycle Policy and MPI Release Types. To learn about the MPI version numbering scheme, see MPI Version Numbering for details.

SynqNet Slice I/O

SynqNet has been expanded to support Slice digital and analog I/O nodes. Slice I/O nodes are modular, which makes it possible to scale the number of digital and analog I/O to fit your application.

For more information see:
      Slice I/O Hardware
      Overview of MPI I/O

SynqNet Dual String Network

SynqNet has been expanded to support Dual String networks. A Dual String topology is a single SynqNet network with nodes connected to both the controller's OUT port and IN port. The Dual String topology is useful for systems with physical layouts that make Ring or String cable routing difficult or impossible. It is also useful for discovering nodes that are downstream from a cable break or failed node.

Example 1
Suppose a system has two nodes and each node must be located 200 meters apart. Since the maximum single connection cable length is 100 meters, the only way to connect both nodes to one controller is to use a dual-string topology. The controller would be located in the middle with a 100 meter cable connected to each node.

Example 2
Suppose a system has two nodes in a ring topology, but the cable is broken between Node 0 and 1. In previous releases, during network initialization, the controller would only discover Node 0 in a String topology. Now, the controller will discover Node 0 and 1 in a Dual-String topology. This makes it possible for an application to use the nodes located both upstream and downstream from a hardware failure.
NOTE: The node addresses are ordered differently for the controller's "out" and "in" port nodes.

For more information see:
     SynqNet Topologies
     SynqNet Node, Cable, Motor, Drive Addressing

The MPI's SynqNet Info structures were expanded to support Dual String topologies and methods were added to traverse the network objects. The new traversal methods will work with future network topologies (trees, ring of rings, etc.). For more information, see the 03.03.00 Release Note.

SynqNet Packet Schedule Improvements

The SynqNet packet scheduling algorithm has been improved for networks with sample rates = 16 kHz or higher, when all the nodes are RMBs (not drive nodes). The scheduling changes will affect the control latency for these systems. For more details see the 03.03.00 Release Note.

Whenever your SynqNet system configuration is changed, you should verify the control latency. SynqNet schedules adapt to hardware changes (controller type, number of nodes, node types, topology, and cable length). Future software releases may have improvements to the schedule algorithms. To ensure hardware and/or software changes, do not change the control loop behavior; verify that the overall control latency remains identical.

For more information see:
     SynqNet Timing Values

To view the SynqNet timing values, see the SqTiming1.c sample application. If control latency is affected, it may be possible to compensate by configuring a different TxTime value. Contact MEI for additional help.

Motor I/O Expansion

The motor digital I/O has been expanded from 32 bits to 64 bits. In previous releases, each motor had a digital I/O word, with the lower 16 bits for dedicated I/O and the upper 16 bits for general purpose I/O. Now, each motor has two words—one for dedicated and one for general purpose I/O.

In version 03.02.00, new methods and bit defines were added to read, write, and identify the motor's digital I/O. These new methods were added in preparation for the motor I/O expansion in the 03.03.00 MPI release. For more information, see Transitioning to the New Motor I/O Functions. The old motor I/O methods and defines were moved to meiDeprecated.h for backwards compatibility.

MPI changes were made to support the new motor I/O words for the following features:
     Sequences: 03.03.00 Release Note
     Motion Hold: 03.03.00 Release Note

In cases where your application directly addresses the motor I/O word, you will need to make application changes. The most common case is Motor User Limits. The translation between the addresses and bits are:

Old Address
New Address
lower 16
upper 16
lower 16
upper 16


See Also: usrLim1.c

/* OLD Address */
motorEventConfig.Condition[0].SourceAddress =
&firmware->Motor [motorIndex].IO.In.IO; /* input address */ /* NEW Address */ motorEventConfig.Condition[0].SourceAddress =
&firmware->Motor[motorIndex].IO.GeneralIn.IO; /* General purpose motor input address */

E-Stop Modify Action

The new E-Stop Modify Action (MPIActionE_STOP_MODIFY), allows the controller to modify a motion profile when the action occurs. By default, the controller will decelerate the axis to zero velocity using an S-Curve deceleration profile. This feature is useful for applications that don't care about stopping on path (MPIActionSTOP or MPIActionE_STOP) or want to optimize the deceleration profile for smoothness. For more information, see the 03.03.00 Release Note.

Host Service Object

A new Host Service Object was added to the apputil library to support the Host/Controller synchronization interrupt. The controller can be configured to generate an interrupt to the Host every "N" sample periods. The Host Service Object provides a simple interface to create a Host Service thread, to execute a user function on a host synchronization interrupt. For more information, see the 03.03.00 Release Note.

Glentek Drive Firmware Download

Drive firmware download via SynqNet is now supported with the Glentek Omega drives. To use this feature, you will need Omega drive hardware rev C (or later). Previous drive hardware only supports Node Runtime FPGA download via SynqNet. Please contact Glentek for the drive firmware files and latest version information.

Node FPGAs

This release includes new SynqNet Node FPGA Runtime images. These images contain some internal improvements and bug fixes. Please see the 03.03.00 FPGA Release Note for more details. MEI always recommends that you use the FPGA images included with the software release.


ZMP Boot0 Image/Firmware Compatibility

WARNING! ZMP-SynqNet series controllers with Boot0 image version 1.002 are ONLY compatible with firmware version 561C2 (or higher). The 561C2 firmware is available with the MPI package version 03.02.06 (or higher). ZMP-Series controllers revision P.5 and greater shipped after May 5th, 2005 have Boot0 image version 1.002 (or higher). Firmware versions 561C1 or older are no longer supported by ZMP-SynqNet series controllers. For more information, please see issue MPI 1666 - Missing foreground cycles on ZMP-SynqNet controllers.

To view the Boot0 version, use the version.exe utility:

If your ZMP-SynqNet series controller is revision P.4 or earlier and has a Boot0 image version that is 1.001 (or lower), it must be returned to MEI for an upgrade. Please contact MEI for more details.


SynqNet Recovery Fails when Topology is Saved

The following controller firmware versions have a bug that causes SynqNet fault recovery to fail if the topology has been saved:

  • 575A2 to 575A5
  • 580A1 to 580A7
  • 582A4

To correct the problem, use firmware version 580B1 (or later), which is available in the 03.03.03 (or later) release package. For more information, please see MPI1817.





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