Release Note
C0FE0034_xxxx.sff

Problem/Cause:
The pulse engine (step/direction logic) may appear to have a momentary position error after network packet errors (or fault recovery). The FPGA pulseFeedback value was not updated when DEMAND packet errors occurred. The "old" pulseFeedback value was sent back to the controller until valid DEMAND packets arrived, which may look like zero velocity to the controller. If a fault recovery is in progress, and the controller does not receive the FEEDBACK packet, the controller will interpolate the expected position based on constant velocity, then at the end of recovery, the controller may get one FEEDBACK packet with "old" pulseFeedback position (correct pulseFeedback will arrive in subsequent packets). This issue existed in all FPGAs prior to version x0345.

Fix/Solution:
The FPGA code was corrected in versions x0345 and later. No software changes are required.

Description:
Add support for multiple packets to the rxMiiBuffer. This improves tolerance to network jitter. Prior to version x0341, the rxMiiBuffer could absorb up to 32 clocks (1.28 µS) of delay for a single packet, but only 8 clocks for multiple packets with minimum spacing. This change is required to meet theoretical worst-case network jitter in large networks (32 nodes). The improvement may also help at network startup, since the node's PLL phase error is larger than normal (as the PLL pulls into nominal lock). No software changes are required.

Description:
Add BranchRev register. This extends the existing 16 bits of FPGA version number with 8 bits of branch and 8 bits of revision ID.

Description:
Release new FPGA type C0FE0034_0340.sff.