Release Note
C0FE002C_xxxx.sff

Description:
A mistake introduced in a recent version of the FPGA source code prevented the FeedbackSsi clock from reaching the gpio pins of the FPGA. This problem has beed fixed. No other FPGA images were affected.

Description:
Expand the dedicatedIn word from 16 bits to 32 bits and add the status bits Feedback 0 Fault and Feedback 1 Fault. Note: Although the FPGAs now supports additional bits, the MPI does not yet enable them.

Problem/Cause:
Clearing the driveWatchdogFault and driveChecksumError required two service comands—a write to start the clear, and a write to end the clear. MPI releases prior to the 03.01.00 did not clear the bits.

Fix/Solution:
Corrected the Drive Watchdog Fault and Drive Checksum Error bits to clear with a single service command. MPI releases 03.01.00 and later support this new behavior and clear the bits after a network reset.

Description:
Set unused pins to FLOAT after the FPGA configuration process. After a power-on, but prior to FPGA configuration, SynqNet FPGA pins should be high-impedance outputs.

NOTE: The mode pins can enable internal pullups, but this is not recommended for SynqNet.

After configuration, unused pins will be high-impedance outputs with no internal pull-up or pulldown. In earlier versions, unused pins would default to weak internal pulldowns. This was not ideal since it could have conflicted with an external pull-up.

Problem/Cause:
There was a problem where SqMax NodeStatus cyclic status bits may have been corrupted after reading some of the FPGA registers (via the service command). The bits that could have been corrupted are: analogPowerFault, ioAbort, nodeAlarm, and nodeDisable. This issue has existed since release x0100.

Fix/Solution:
This problem has been fixed.

Description:
Support has been added for a number of different flash component vendors. Flash components that are currently supported are:

Problem/Cause:
There was a problem with the inverted polarity option for the FPGA inputs nodeDisable and analogPowerFault. Prior to this fix, only the default polarity was functional. The problem happened because the hardware invert logic was inserted after the hardware latch function. Therefore, when "invert" was selected, the input would typically latch the negated state, and would not report a fault unless the latch was cleared by a software command. If the "invert" option was NOT used, the input would function correctly. This issue did not exist until the x020C release, where these inputs were first latched.

Fix/Solution:
This problem has been fixed.

Problem/Cause:
There was a problem in the sqPll function of the sqMac. With certain timing values, one node in the network may have fail to hold lock and then aborts cyclic operation. For a typical 3-node network, this timing typically occurred with TxTime set to 95%. Other TxTime values may fail in other network configurations.

Fix/Solution:
This problem has been fixed.

Description:
The drive current of GPIO pins has been increased to +/-24mA. Other outputs which may drive opto isolators (LED outputs, nodeAlarm, ampEnable, brakeApplied) were already configured for 24mA drive current. See individual FPGA specifications for complete details of I/O characteristics.

Problem/Cause:
There was a problem in the receive data unload function of the sqMax. In certain situations where the packet size did not match the configured packet size, invalid sqMax outputs were observed to cause "glitches" in the I/O output signals. The glitches would occur at the transition from cyclic to asynq operation, but the ioAbort signal would normally prevent these glitches from reaching external logic.

Fix/Solution:
This problem has been fixed.

Description:
Improvements have been made to the secondary encoder features. These changes allow the use of encoder faults and capture with secondary encoders. Secondary feedback for drives has also been added. The changes are NOT backwards compatible with software releases prior to 20031222 (secondary encoder feedback is not fully functional with prior software).

Description:
Improvements have been made to the ADC features to use the new "nodeIo" conventions. These changes allow up to 8 ADC channels per node (prior to this, the default was 1 ADC channel per motor). The changes are NOT backwards compatible with software releases prior to 20031222 (ADCs are not functional with prior software).