Signaling Method

A detailed description of the signaling method can be found in ANSI X3.263-1995 and IEEE 802.3-1998 Clauses 24-26. However, a brief summary is provided below.

The signaling scheme is strictly point-to-point, i.e. one transmitter is connected to one receiver. Each link is full duplex, i.e. capable of transmitting and receiving simultaneously. The electronic component sited at each end of the link is known as a PHY. A typical setup is illustrated below:

The data is presented to and retrieved from the PHY on separate four-bit wide data paths.

The PHY block itself is a complex device. Data is accepted as 'nibbles' at a rate of 25MHz. Each nibble is mapped from a four-bit data set to a five-bit symbol. This type of mapping ensures that there are sufficient transitions to permit clock recovery and it also allows control symbols to be transmitted. The symbols are then scrambled to avoid peaks in the emission spectrum from the cabling. The scrambled symbols are then converted to a serial bit-stream that is NRZI encoded (transitions on 1s; no transitions on 0s) so as to lower the edge rate. Finally, this bit stream is presented to the copper twisted pair or fiber as appropriate. The receive process is naturally the reverse of the transmit process.

The transmit process is illustrated below:

The PHY is also responsible for ensuring the correct byte alignment. In addition to data symbols, the PHY supports the following control symbols:

Symbol Name	Meaning
/H	HALT, transmitted to indicate a fault condition such as a bad packet
/I	IDLE, transmitted when there is no packet to transmit
/J/K	SSD, two symbols used to indicate the start of a packet
/T/R	ESD, two symbols used to indicate the end of a packet

In its inactive condition the transmitter sends IDLE symbols, which ensures that the receiver is provided with transitions so that clock recovery can occur correctly at the receiver.

The IDLE symbols are also necessary to ensure that the descrambler can be trained to operate correctly at the receiver. The scrambler is guaranteed (ANSI X3.263-1995 Clause 7.2.3.2.2) to acquire synchronization after 30 error free bits including several IDLEs and /J /K (i.e. four IDLE symbols before the start of transmission). The PHY will detect an error condition (ANSI X3.263-1995 Clause 7.2.3.3) if four IDLE symbols are not found within each 1.5ms period. Some PHY watchdogs are stricter and require eight or even twelve IDLE symbols every 722ms (8k bytes). SynqNet fulfils this requirement during the SYNQ network operational phase by ensuring that sufficient idle time is present per communication cycle. As a result, 2kHz is the minimum cyclic rate, unless other measures are taken to insert IDLEs.