Interface to the MAC
There are three interfaces between the MAC and the PHY: SMI, Transmit, and Receive.
Collectively they are referred to as the MII and are defined in IEEE 802.3-1998 Clause 22.
Transmit is a nibble wide interface that is clocked by a local 25MHz clock. The clock must always be present. If there is nothing to transmit then the TXEN line is inactive and the PHY automatically transmits IDLE symbols.
Receive is a nibble wide interface that reconstructs its clock from the received bit stream.
The SMI (serial management interface) provides a standardized method of accessing the registers within the PHY via a two-wire interface. The basic and extended register sets are defined in IEEE 802.3-1998 Clause 22. Some PHYs may support additional registers.
The SMI interface is currently not required for SynqNet, and is reserved for future use.