.

Rear I/O Bus Connection

    

For applications utilizing industry standard CPCI 6U, MEI can provide the following pinouts.

Pin
E
D
C
B
A
Pin
19
No Connect No Connect Gnd No Connect No Connect
19
18
No Connect No Connect Gnd No Connect No Connect
18
17
No Connect No Connect Gnd No Connect No Connect
17
16
Opto_F_Rtn Opto_F Gnd Opto_A_RTN OPTO_A
16
15
UserIO_B3_RTN UserIO_B3 Gnd UserIO_A3_Rtn UserIO_A3
15
14
Opto_E_RTN Opto_E Gnd Reset_IN XESTOP
14
13
Opto_C Opto_C_RTN Gnd Opto_B_RTN OPTO_B
13
12
No Connect No Connect Opto_D_RTN No Connect XESTOP_RTN
12
11
No Connect No Connect Opto_D No Connect No Connect
11
10
No Connect No Connect No Connect No Connect No Connect
10
9
No Connect No Connect No Connect No Connect No Connect
9
8
No Connect No Connect No Connect No Connect No Connect
8
7
No Connect No Connect No Connect No Connect No Connect
7
6
Gnd Gnd Gnd Gnd Gnd
6
5
SynqRec_OUT+ SynqRec_OUT– No Connect SynqTrancs_OUT+ SynqTrans_OUT–
5
4
3_3V 3_3V 3_3V Gnd Gnd
4
3
SynqRec_IN+ SynqRec_IN– No Connect SynqTrancs_IN+ SynqTrans_IN–
3
2
Gnd Gnd Gnd Gnd Gnd
2
1
Can_Hrp Can_LRP No Connect Can_Grp Can_VRP
1
Pin
E
D
C
B
A
Pin

Location of Rear I/O on XMP-SynqNet-CPCI-Rear I/O (T001-0005)

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