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ADC Sample Period

The ADC Sample Period is the maximum time required to sample all enabled analog inputs (ADC channels).

RMB-10V2-SynqNet ADC channels are normally sampled once per controller cycle. If the controller cycle is shorter than the ADC period, then the analog inputs are sampled every Nth controller cycle (where N * controller period > ADC period). Inputs are sampled sequentially, starting with channel 0. The number of inputs to sample can be configured by software. For RMB-10V2-SynqNet, the default is all 4 inputs.

The following calculation determines the ADC Sample Period:

 

MaxAdcPeriod = (EnabledChannels * 13.08 µS) – 3 µS


Enabled Channels
ADC Sample Period
1
10.08 µS
2
23.16 µS
3
36.24 µS
4
49.32 µS
(default for RMB-10V2-SynqNet)

The ADC sample jitter is very small, although there may be some variation between different nodes. The sample time of ADC channel 0 is derived from the node's network timer,
which has very low jitter (+/- 40 nS per cycle typical). Subsequent conversion cycles for channels 1, 2, 3 are delayed by the ADC's "busy" output. This is expected to be very consistent (+/- 100 nS per conversion) on any given RMB-10V2-SynqNet, but may vary between two different nodes.

 

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