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SQIO LatencySPI Rate  SPI Delay  SynqNet Delay Digital Inputs  Digital Outputs  Analog Inputs  Analog Outputs SPI RateThe SPI rates on the digital input SPI, digital output SPI, analog input SPI and analog output SPI are completely independent. There are four impendent SPI busses numbered SPI0, SPI1, SPI2 and SPI3, resepctively. Connecting ADC4DAC4 to and existing assembly of SQI+DIN32DOUT32 will not affect the SPI rate of either. However, when a unit with an MM1 is connected to a DIN32DOUT32, the lesser clock rate will prevail on the affected SPIs; in this case SPI0 and SPI1.
SPI DelayThe SPI Delay, which is the number of bits divided by the clock rate (default 6.25MHz) plus 2µs, is tabulated in Table 1 below. SPI Delay = (Number of bits / SPI Clock Rate) + 2µs
SynqNet DelayThe worstcase SynqNet Delay is:
Here is the equation for the worst case offlatency for a 256input node, with an SPI clock rate of 6.25MHz and a SynqNet cyclic rate of 2kHz: Worstcase OFFlatency = Optoisolator Delay + SPI Delay + SynqNet Delay and the worst case onlatency under the same conditions is: Worstcase ONlatency = Optoisolator Delay + SPI Delay + SynqNet Delay If the (SynqNet Delay) < (SPI Delay) then the input conversion will occur less frequently than the SynqNet cyclic rate and will require an additional delay of an integral number of SynqNet cycle times.
Digital InputsHere is the equation for the worstcase latency between an input voltage changing and the value appearing at the motion controller: Worstcase Latency = Optoisolator Delay + SPI Delay + SynqNet Delay For a standard optoisolator, the delay is 1µs when the input is energized and 500µs when the input is deenergized.
Digital OutputsHere is the equation for the worstcase latency between the value sent from the motion controller and the respective change in output voltage: Worstcase Latency = Optoisolator Delay + SPI Delay + SynqNet Delay For a standard Darlington optoisolator, the delay is 5µs when the output is turned ON and 80µs when the output is turned OFF, which will depend on the load current. The SPI Delay is shown in Table 1 and the SynqNet Delay in Table 2. Here is the equation for the worst case onlatency for a 256output node, with an SPI clock of 6.25MHz and a SynqNet cyclic rate of 2kHz: Worstcase ONlatency = Optoisolator Delay + SPI Delay + SynqNet Delay and the worst case offlatency under the same conditions is: Worstcase OFFlatency = Optoisolator Delay + SPI Delay + SynqNet Delay If the SynqNet Delay < (Optoisolator Delay + SPI Delay) then the output update will occur less frequently than the SynqNet cyclic rate and will require an additional delay of an integral number of SynqNet cycle times.
Analog InputsHere is the equation for the worstcase latency between an input voltage changing and the value appearing at the motion controller: Worstcase Latency The standard ADC conversion time is 8µs for all ADC4DAC4 and MM1 modules. The SPI Delay is tabulated in Table 3 below.
The SynqNet Delay in calculated in Table 2. So, the worst case onlatency for a 16 ADC input node, with an SPI clock of 6.25MHz and a SynqNet cyclic rate of 2kHz: Worstcase Latency Again, if the (SynqNet delay) < (ADC conversion time * number of channels) + (SPI delay) then the input conversion will occur less frequently than the SynqNet cyclic rate and will require an additional delay of an integral number of SynqNet cycle times. For example, if the cyclic rate were increased to 6kHz in the above example, then the conversion would occur every other cycle and the total latency would be: Total Latency at 6kHz whereas at an 4kHz cyclic rate, the total latency would be: Total Latency at 4kHz = i.e. the latency is shorter at the lower SynqNet cyclic rate. In practice, the double buffering that leads to this paradoxical result occurs only with very high SynqNet cyclic rates in combination with large I/O sets.

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