SQIO Latency

Digital Inputs | Digital Outputs | Analog Inputs | Analog Outputs

SPI Rate

The SPI rates on the digital input SPI, digital output SPI, analog input SPI and analog output SPI are completely independent. There are four impendent SPI busses numbered SPI0, SPI1, SPI2 and SPI3, resepctively. Connecting ADC4DAC4 to and existing assembly of SQI+DIN32DOUT32 will not affect the SPI rate of either.

However, when a unit with an MM1 is connected to a DIN32DOUT32, the lesser clock rate will prevail on the affected SPIs; in this case SPI0 and SPI1.

Module	SPI Rate
DIN32DOUT32	6.25MHz
ADC4DAC4	6.25MHz
MixedModule1	12.5MHz

SPI Delay

The SPI Delay, which is the number of bits divided by the clock rate (default 6.25MHz) plus 2µs, is tabulated in Table 1 below.

SPI Delay = (Number of bits / SPI Clock Rate) + 2µs

Table 1 SPI delay for digital I/O (in micro-seconds)
SPI Clock Rate (MHz)	Number of Bits on Relevant SPI
SPI Clock Rate (MHz)	32	64	128	256	512
3.125	12.24	22.48	42.96	83.92	165.84
6.25	7.12	12.24	22.48	42.96	83.92
12.5	4.56	7.12	12.24	22.48	42.96

SynqNet Delay

The worst-case SynqNet Delay is:

2	500
Table 2 Cyclic Rate vs. Latency
Cyclic Rate (kHz)	Latency (µs)
3.2	312.5
4	250
8	125
16	62.5

Here is the equation for the worst case off-latency for a 256-input node, with an SPI clock rate of 6.25MHz and a SynqNet cyclic rate of 2kHz:

          Worst-case OFF-latency = Opto-isolator Delay + SPI Delay + SynqNet Delay
                                               =            500              +     42.96      +       500
                                               = 1042.96µs

and the worst case on-latency under the same conditions is:

          Worst-case ON-latency = Opto-isolator Delay + SPI Delay + SynqNet Delay
                                             =                1              +      42.96    +           500
                                             = 543.96µs

If the (SynqNet Delay) < (SPI Delay) then the input conversion will occur less frequently than the SynqNet cyclic rate and will require an additional delay of an integral number of SynqNet cycle times.

Digital Inputs

Here is the equation for the worst-case latency between an input voltage changing and the value appearing at the motion controller:

Worst-case Latency = Opto-isolator Delay + SPI Delay + SynqNet Delay

For a standard opto-isolator, the delay is 1µs when the input is energized and 500µs when the input is de-energized.

Digital Outputs

Here is the equation for the worst-case latency between the value sent from the motion controller and the respective change in output voltage:

Worst-case Latency = Opto-isolator Delay + SPI Delay + SynqNet Delay

For a standard Darlington opto-isolator, the delay is 5µs when the output is turned ON and 80µs when the output is turned OFF, which will depend on the load current.

The SPI Delay is shown in Table 1 and the SynqNet Delay in Table 2.

Here is the equation for the worst case on-latency for a 256-output node, with an SPI clock of 6.25MHz and a SynqNet cyclic rate of 2kHz:

          Worst-case ON-latency = Opto-isolator Delay + SPI Delay + SynqNet Delay
                                             =               5             +    42.96     +        500
                                             = 547.96µs

and the worst case off-latency under the same conditions is:

          Worst-case OFF-latency = Opto-isolator Delay + SPI Delay + SynqNet Delay
                                               =             80             +    42.96     +        500
                                               = 622.96µs

If the SynqNet Delay < (Opto-isolator Delay + SPI Delay) then the output update will occur less frequently than the SynqNet cyclic rate and will require an additional delay of an integral number of SynqNet cycle times.

Analog Inputs

Here is the equation for the worst-case latency between an input voltage changing and the value appearing at the motion controller:

Worst-case Latency
= [(ADC Conversion Time * Number of Channels) + SPI Delay] + SynqNet Delay

The standard ADC conversion time is 8µs for all ADC4DAC4 and MM1 modules.

The SPI Delay is tabulated in Table 3 below.

Table 3 SPI delay for analog channels
SPI Clock (MHz)	Number of Analog Channels
SPI Clock (MHz)	1	2	4	8	16	32
3.125	7.12	12.24	22.48	42.96	83.92	165.84
6.25	4.56	7.12	12.24	22.48	42.96	83.92
12.5	3.28	4.56	7.12	12.24	22.48	42.96

The SynqNet Delay in calculated in Table 2.

So, the worst case on-latency for a 16 ADC input node, with an SPI clock of 6.25MHz and a SynqNet cyclic rate of 2kHz:

Worst-case Latency
        = [(ADC Conversion Time * Number of Channels) + SPI Delay] + SynqNet Delay
        =                               [(8 * 16)                          +    42.96]     +          500
        =                                                      [170.96]                       +          500
        = 670.96µs

Again, if the (SynqNet delay) < (ADC conversion time * number of channels) + (SPI delay) then the input conversion will occur less frequently than the SynqNet cyclic rate and will require an additional delay of an integral number of SynqNet cycle times. For example, if the cyclic rate were increased to 6kHz in the above example, then the conversion would occur every other cycle and the total latency would be:

Total Latency at 6kHz
         = [(ADC Conversion Time * Number of Channels) + SPI Delay] + SynqNet Delay
         =                              [(8 * 16)                          +     42.96]   +     (2 * 166.66)
         =                                                      [170.96]                       +      333.33
         = 504.29µs

whereas at an 4kHz cyclic rate, the total latency would be:

Total Latency at 4kHz =
         = [(ADC Conversion Time * Number of Channels) + SPI Delay] + SynqNet Delay
         =                               [(8 * 16)                          +      42.96]   +        250
         =                                                      [170.96]                       +        250
         = 420.96µs

i.e. the latency is shorter at the lower SynqNet cyclic rate.

In practice, the double buffering that leads to this paradoxical result occurs only with very high SynqNet cyclic rates in combination with large I/O sets.

Analog Outputs

Here is the equation for the worst-case latency between the value sent from the motion controller and the respective change in output voltage:

Worst-case Latency = SynqNet Delay + SPI Delay + Slew Rate Delay

The slew-rate delay varies with the change of voltage, but for most purposes a lumped figure of 10µs can be used.

The SynqNet Delay is in Table 2.
The SPI Delay is in Table 3.

Here is the equation for the worst case on-latency for an 8 DAC node, with an SPI clock of 6.25MHz and a SynqNet cyclic rate of 2kHz:

          Worst-case ON-latency = Slew Rate Delay + SPI Delay + SynqNet Delay
                                             =          10             +    22.48    +         500
                                             = 532.48µs

If the (SynqNet delay) < (SPI delay) then the output update will occur less frequently than the SynqNet cyclic rate and will require an additional delay of an integral number of SynqNet cycle times.