.

Release Note
C0FE0036_xxxx.sff

MPI Version
FPGA Version
03.04.17
C0FE0036_0400_02_10
03.04.16
C0FE0036_0400_02_0F
NA
C0FE0036_0400_02_0E
03.04.13
C0FE0036_0400_02_0D
NA
C0FE0036_0400_02_0C
03.04.08
C0FE0036_0400_02_0A
03.04.05
C0FE0036_0400_02_08
03.04.04
C0FE0036_0400_02_07
03.04.03
C0FE0036_0400_02_06
03.04.02
C0FE0036_0400_02_05
03.04.01
C0FE0036_0400_02_04
03.04.00
Production Release
C0FE0036_0400_02_01
03.03.00
Production Release
C0FE0036_0346_00_02
03.02.00
Production Release
C0FE0036_0344

  Table of Contents
     
    Changes and Bug Fixes
     

C0FE0036_0400_02_10
     S200 Mitutoyo encoder fault - Bug Fix - FP883

C0FE0036_0400_02_0F
     Mitutoyo feedback option - New Feature - FP862

C0FE0036_0400_02_0E
     drivePll fails to lock at 1090 Hz controller, 24 kHz drive - Bug - FP860

C0FE0036_0400_02_0D
     Endat 2.2 analog compatibility - New Feature - FP793
     Custom feedback type - New Feature - FP794
     1 Vp-p Sin-Cos feedback recovery improvement - New Feature - FP816
     Unused logic (compare and GPIO muxes) - General Change - FP791

C0FE0036_0400_02_0C
     Updated drivePll - General Change - FP756

C0FE0036_0400_02_0A
     EnDat absolute encoder initialization offset - Bug Fix - FP745
     Sin/Cos option for S200 drive - New Feature - FP720

C0FE0036_0400_02_09
     Support for Drive Gain Scheduling on S200 drive - New Feature - FP704

C0FE0036_0400_02_08
     Support for ENDAT Encoder EEPROM access - New Feature - FP669

C0FE0036_0400_02_07
     Addition of Commutation Offset - New Feature - FP656

C0FE0036_0400_02_06
     S200 monitor pointers sometimes return 0x0 when read - Bug Fix - FP601

C0FE0036_0400_02_05
     Absolute Encoder Initialization - Bug Fix - FP566

C0FE0036_0400_02_04
     Monitor A/B/C pointer corruption - Bug Fix - FP548

C0FE0036_0400_02_03
     Improvements to AuxFB synchronization - General Change - FP546

C0FE0036_0400_02_02
     driveInterfaceParallelMaster - incorrect service read data - Bug Fix - FP542
     Addition of signal brakeDriveFlag and update readyForRemoteControl logic - Bug Fix - FP523

C0FE0036_0400_02_01
     Bug in service channel causes corrupt data to be written to the base unit - Bug Fix - FP518

C0FE0036_0400_02_00
     Modify service channel to update base unit once per handshake - General Change - FP514
     Addition of filters on home, posLimit, and negLimit inputs - New Feature - FP512
     sqNodeParallelMasterTopChip - Addition of filters - New Feature - FP502

C0FE0036_0400_00_03
     Connect driveStatusFlag9, driveStatus10 between driveMemory and dedicatedIo - Bug Fix - FP394
     Addition of nodeIoSliceFault in order to exit the CYCLIC_STOP_HOLD state - Bug Fix - FP387

C0FE0036_0400_00_02
     Change DEMAND_A and DEMAND_B data destinations for velocity mode - New Feature - FP490

C0FE0036_0400
     Remove drive reset complete from the fault and fault mask registers - General Change - FP466 
     The watchdog fault was incorrectly being cleared after being activated - Bug Fix- FP465
     sqMac Build 0300 - New Feature - FP407
     Update the encoder word to 8-bits of multi-turn data and 24-bits of revolution data - General Change - FP405
     Latch added on the notAmpPowered bit - General Change - FP402
     Removal of adcGp module; addition of auxfb2_tb module - New Feature - FP392
     Support for a maximum count rate of 50MHz without filters - New Feature - FP337

C0FE0036_0346_00_02
     Drive monitor A/B/C pointers corrupted on driveInterfaceParallelMaster - Bug Fix - FP366

C0FE0036_0346_00_01
     Fix drive fault clear for driveInterfaceParallelMaster - Bug Fix - FP360

C0FE0036_0346
     Modifications to gpioPinConfigReg - General Change - FP336
     Intermittent Dual String Discovery failure - Bug Fix - FP332
     sqMac - 0x00 will be read for dataType NULL - New Feature - FP323
     Intermittent Fault Recovery failures - Bug Fix - FP315
     Changed the pin location for gpio0_z[2] and number of gpioBits - General Change - FP307

C0FE0036_0344
     Block nodeAlarm to the drive if a driveFault is occurring - Bug Fix - FP285

C0FE0036_0341
     sqMac rxMiiBuffer multiple packets - General Change - FP263
     New FPGA C0FE0036 - General Change - FP243

C0FE0036_0340
     New BranchRev Register - New Feature - FP231


C0FE0036_0400_02_10

  S200 Mitutoyo encoder fault
    Reference Number: FP 883
    Type: Bug Fix
    FPGA Version: 0x0400_02_10
   

Problem/Cause:

Mitutoyo encoder fault does not cause drive fault, and therefore no MPI ampFault event.

The internal FPGA encoder logic detects faults correctly, but the fault status is not OR-ed into the general drive fault status.

   

Fix/Solution:
The FPGA logic was corrected allowing the fault status to OR into the general fault drive status.


C0FE0036_0400_02_0F

  Mitutoyo feedback option
    Reference Number: FP 862
    Type: New Feature
    FPGA Version: 0x0400_02_0F
    Description:
Adds support for Mitutoyo serial digital interface rotary, linear, and absolute encoders.


C0FE0036_0400_02_0E

  drivePll fails to lock at 1090 Hz controller, 24 kHz drive
    Reference Number: FP 860
    Type: Bug Fix
    FPGA Version: 0x0400_02_0E
   

Problem/Cause:
The drivePll may fail to lock for some unusual drive:controller ratios such as 22:1 (for example, 24 kHz drive with 1090 Hz controller). Drive communication will not be enabled. It is not possible to enable the drive. Motor status typically indicates Amp_Fault.

For certain controller rates, the MPI roundoff results in errors outside the drivePll phase detection range and the drivePll fails to lock.

   

Fix/Solution:

The drivePll module in the FPGA source code was upgraded with a phase detect range of +/-31 counts, which will support any drive:controller ratio from 1:1 to 32:1 (drive rates up to 32 kHz and controller rates down to 1 kHz).


C0FE0036_0400_02_0D

  Endat 2.2 analog capability
    Reference Number: FP 793
    Type: New Feature
    FPGA Version: 0x0400_02_0D
   

Description:
EnDat interface now supports EnDat 2.2 rotary and linear including absolute devices operating in EnDat 2.1 compatibility mode. The S200 SynqNet supports Aux feedback if the EnDat 2.2 encoder has 1 Vp-p analog outputs. Example devices are Heidenhain LC183 and LC182 EnDat 2.2 absolute linear encoders.


  Custom feedback type
    Reference Number: FP 794
    Type: New Feature
    FPGA Version: 0x0400_02_0D
   

Description:

Custom feedback type was added.

Note: This feature is reserved for future use.


  1 Vp-p Sin-Cos feedback recovery improvement
    Reference Number: FP 816
    Type: New Feature
    FPGA Version: 0x0400_02_0D
   

Description:
Improved recovery from overload or loss of synchronization for 1 Vp-p Sin-Cos feedback on J14.


  Unused logic (compare and GPIO muxes)
    Reference Number: FP 791
    Type: General Change
    FPGA Version: 0x0400_02_0D
   

Description:

Unused logic was removed from the FPGA to make space for other features. The compare module was never supported by software and is therefore removed. Since only one GPIO pin is an S200 output (GPIO bit 2, OOUT1), all other output muxes were removed.


C0FE0036_0400_02_0C

  Updated drivePll module
    Reference Number: FP 756
    Type: General Change
    FPGA Version: 0x0400_02_0C
   

Description:
The drivePll module was improved to lock for a wider range of driveUpdatePeriod:controllerPeriod ratios and greater initial period error. This upgrade allows up to a 32:1 ratio and initial error of up to 16 clocks (0.640 us). This upgrade will reliably lock for any drive update period or controller period supported in any software release to date. Prior to this upgrade, the drive interface for some nodes failed to lock for some controller sample rates.

For example, a drive with 16 kHz period (such as S200) would not reliably lock to the controller rate of 1066 Hz. This configuration has a 15:1 driveUpdatePeriod:controllerPeriod ratio, and for various software reasons has a larger-than-normal initial period error. Problem ratios (and controller periods assuming a 16 kHz drive update period) are: 15:1 (1066 Hz), 14:1 (1142 Hz), 13:1 (1230 Hz). Marginal ratios are: 12:1 (1333 Hz), 11:1 (1454 Hz), 9:1 (1777 Hz), and 7:1 (2285 Hz). The marginal ratios may fail depending on the accuracy of the controller and node oscillators. When drivePll acquistion fails, the drive will not get the cyclic flag Drive_Strobe_Lock=1, and will not return the cyclic status Drive_Ready=1. The motor status indicates Amp_Fault and the motor cannot be enabled.

C0FE0036_0400_02_0A

  EnDat absolute encoder initialization offset
    Reference Number: FP 745
    Type: Bug Fix
    FPGA Version: 0x0400_02_0A
   

Problem/Cause:
The S200 EnDat encoder logic may have position offset errors at initialization under some conditions. The result may appear as a position "jump" to the user or application. This only occurs when:

  1. EnDat 2.1 encoder feedback is used
  2. Feedback is changing
  3. SynqNet initialization (or controller reset) occurs
    Fix/Solution:
This logic bug was fixed in the FPGA source code in the sqAuxfb Build 0020 added to 0400_02 branch lib tree.

  Sin/Cos option for S200 drive
    Reference Number: FP 720
    Type: New Feature
    FPGA Version: 0x0400_02_0A
    Description:
A test option has been added to the S200 sin/cos (endat) encoder interface.
This feature is reserved for future use and defaults to OFF on reset.

 

C0FE0036_0400_02_09

  Support for Drive Gain Scheduling on S200 drive
    Reference Number: FP 704
    Type: New Feature
    FPGA Version: 0x0400_02_09
    Description:
S200 drive gains KVP and KVI will switch based on 3-bit gain index sent each SynqNet cycle with demand data. The controller uses the same gain index for internal gain tables and for drive gains. See Gain Tables for further details on controller software. See the S200 drive documentation for further details on KVP and KVI.

 

C0FE0036_0400_02_08

  Support for ENDAT Encoder EEPROM access
    Reference Number: FP 669
    Type: New Feature
    FPGA Version: 0x0400_02_08
    Description:
C0FE0036 now supports Endat Encoder EEPROM access. This will be used to store homing position data. This feature is backwards compatible with prior hardware and software.

 

C0FE0036_0400_02_07

  Addition of Commutation Offset
    Reference Number: FP 656
    Type: New Feature
    FPGA Version: 0x0400_02_07
    Description:
Support was added for a new demand mode, 0x8 (Custom). When this demand mode is enabled, the SynqNet cyclic data field, Demand_B, is written to the S200 CommutationOffset (CommOff) registers. Demand_B becomes a signed 16-bit integer that represents the commutation offset angle. In the hardware, the lower 4 bits are masked off before writing to the S200 CommutationOffset registers, since those bits correspond to another parameter type. Demand_A (torque) is still written to the S200 CurrentCommand (Command) register.

 

C0FE0036_0400_02_06

  S200 monitor pointers sometimes return 0x0 when read
    Reference Number: FP 601
    Type: Bug Fix
    FPGA Version: 0x0400_02_06
   

Problem/Cause:
When reading the monitor pointer values, the data was not returned through the whole service command handshake. In the FPGA, the data is written into a double buffered dual port memory. Depending upon which buffer the data ends up in, and which buffer the controller reads from, it determines whether or not the pointer value is correctly returned. Whether or not the controller reads the buffer that contained the correct data is dependent upon the network configuration, sample rate and the controller TX time.

    Fix/Solution:
The logic for reading the monitor pointer values was changed to guarantee that the correct data was returned during the whole service command handshake. This guaranteed that the data was written in both portions of the double buffer, thus guaranteeing that the controller would read the correct data.

 

C0FE0036_0400_02_05

  Absolute Encoder Initialization
    Reference Number: FP 566
    Type: Bug Fix
    FPGA Version: 0x0400_02_05
    Problem/Cause:
Some absolute encoders would intermittently initialize with a position error up to +/- 6 multi-turn counts.
    Fix/Solution:
This problem was fixed.

 

C0FE0036_0400_02_04

  Monitor A/B/C pointer corruption
    Reference Number: FP 548
    Type: Bug Fix
    FPGA Version: 0x0400_02_04
    Problem/Cause:
Writes to monitor A, B, and C memory pointers did not work correctly. Any value written to a drive monitor resulted in a pointer value of 0x1010. Since the memory pointer was corrupted, invalid cyclic monitor data was returned. A problem was found in the FPGA source code, which allowed the pointer corruption.
   

Fix/Solution:
The source code was corrected for future FPGA versions.

 

C0FE0036_0400_02_03

  Improvements to AuxFB synchronization
    Reference Number: FP 546
    Type: General Change
    FPGA Version: 0x0400_02_03
    Description:
When using AuxFB feedback (sin/cos for example), the time that the position is sampled is now synchronized more exactly to the controller period (it will have less jitter). Also, a fix was made for a register read back for Kollmorgen S200 parameters.

 

C0FE0036_0400_02_02

  driveInterfaceParallelMaster - incorrect service read data
    Reference Number: FP 542
    Type: Bug Fix
    FPGA Version: 0x0400_02_02
    Problem/Cause:
In previous versions, some SynqNet configurations showed different service read results with different controller TX times. The driveInterfaceParallelMaster module was intercepting all read/write accesses from the controller in order to guarantee that they were implemented only once to the drive FPGA. It was found that only one of the buffers in the double buffered drive memory module was being updated with new service read data. Therefore, depending upon SynqNet timing, the service read data could be incorrect.
   

Fix/Solution:
All data from service command reads are now latched in the driveInterfaceParallelMaster module so that they can be written to the double buffered drive memory module every drivePll period.


  Addition of signal brakeDriveFlag and update readyForRemoteControl logic
    Reference Number: FP 523
    Type: Bug Fix
    FPGA Version: 0x0400_02_02
    Problem/Cause:
When the Amp Enable Flag bit was written to the S200, the amplifier was not enabled until 20ms later, during which time the brake would not engage. This was a potential safety issue for customers using the optional brake output function. The S200 Base Unit has an input (DINP1) that may disable the amplifier at any time. When the amplifier is disabled by DINP1, SynqNet was not notified, which caused confusion because the MPI software would report that the amplifier was enabled when in reality, the amplifier was not enabled and the brake was not engaged.
   

Fix/Solution:
Changes have been made so that the Brake Output bit is now enabled whenever the S200 amplifier is disabled. ReadyForRemoteControl (inverse of NotAmpPowered) is now active when either the driveFault or DINP1 is active. There was also a related MPI software change to modify the default state of the fault mask bit for Amp Not Powered. See MPI 1936 for more information.
This bit can also be set from Motion Console (or application) for older MPIs which leave it off by default.

 

C0FE0036_0400_02_01

  Bug in service channel causes corrupt data to be written to the base unit
    Reference Number: FP 518
    Type: Bug Fix
    FPGA Version: 0x0400_02_01
    Problem/Cause:
In FPGA version 0x0400_02_00 only, an invalid service channel transfer could have occurred with a Kollmorgen S200 drive. Typically, the S200 drive would display a fault indication after SynqNet initialization.
   

Fix/Solution:
The FPGA logic has been corrected in FPGA version 0x0400_02_01 and later.

 

C0FE0036_0400_02_00

  Modify service channel to update base unit once per handshake
    Reference Number: FP 514
    Type: General Change
    FPGA Version: 0x0400_02_00
    Problem/Cause:
Prior to FPGA version 0x0400_02_00, the SynqNet service command handshake might have caused multiple consecutive instances of the same read or write transfer to be seen by the Kollmorgen S200 drive base unit. For some multi-byte registers which latched on a particular byte, it was possible to generate an invalid read or write operation. This was observed with S200 GUI transfering one byte at a time. It was not observed with sqDriveParam, which transfered data sizes corresponding to the register size.
   

Fix/Solution:
In FPGA version 0x0400_02_00 and later, the FPGA module was changed to issue only one read or write command to the base unit per service channel access.


  Addition of filters on home, posLimit, and negLimit inputs
    Reference Number: FP 512
    Type: New Feature
    FPGA Version: 0x0400_02_00
   

Description:
On the S200 SynqNet Option card, the home, posLimit, and negLimit inputs use opto isolator inputs with slow rise times to drive FPGA logic. The opto circuits were slow enough to cause glitching in the FPGA while the input value passed through the FPGA input threshold region. This glitching could cause false triggers in the capture engine. To compensate for the slow rise time of the opto isolator inputs, glitch filters were added on home, pos_lim, and neg_lim. The filter blocks pulses less that 35 µs in width (inputs are delayed a minimum of 35 µs, maximum of 41 µs).

For more information, see S200: Open Issues.


  Addition of filters on home, posLimit, and negLimit inputs
    Reference Number: FP 502
    Type: New Feature
    FPGA Version: 0x0400_02_00
   

Description:
On the S200 hardware, the home, posLimit, and negLimit inputs are connected to optos with a slow rise time. The opto circuits are slow enough to cause glitching on the inputs while the input value passed through the "high" threshold region. This glitching could cause false triggers in the capture engine. To compensate for the slow rise time of the opto isolator inputs, glitch filters were added on home, pos_lim, and neg_lim. The filter blocks pulses less that 35µs in width (and delays inputs between 35 – 41µs).

 

C0FE0036_0400_00_03

  Connect driveStatusFlag9, driveStatus10 between driveMemory and dedicatedIo
    Reference Number: FP 394
    Type: Bug Fix
    FPGA Version: 0x0346_00_03; 0x0400
    Problem/Cause:
Prior to FPGA version 0x0346_00_03, and 0x0400 the driveStatusFlag9 and driveStatusFlag10 bits were always forced to "0." These status bits were used for "Autonomous_Drive_Action_Complete" and "Reserved for drive specfic features."
   

Fix/Solution:
In FPGA version 0x0346_00_03, 0x0400 and later, the driveStatusFlag9 and driveStatusFlag10 bits are controlled by the drive processor.


  Addition of nodeIoSliceFault in order to exit the CYCLIC_STOP_HOLD state
    Reference Number: FP 387
    Type: General Change
    FPGA Version: 0x0346_00_03; 0x0400
   

Description:
Prior to FPGA version 0346_00_03 and later, 0400 and later, a nodeIoSliceFault would put the slice network into a "STOP" mode. It would not exit this mode until an unrelated ioAbort event happened and then cleared. Changes have been made so that when the nodeIoSliceFault is now cleared, the nodeIoSlice module will exit this state and resume normal cyclic operation.

 

C0FE0036_0400_00_02

  Change DEMAND_A and DEMAND_B data destinations for velocity mode
    Reference Number: FP 490
    Type: New Feature
    FPGA Version: 0x0400_00_02
    Description:
Version 0x0400_00_02 and later support velocity mode. An MPI software release of 03.04.00 or later is required for velocity mode.

 

C0FE0036_0400

  Remove drive reset complete from the fault and fault mask registers
    Reference Number: FP 466
    Type: General Change
    FPGA Version: 0x0400
    Problem/Cause:
As more drives require a driveBootComplete bit to indicate when they are finished booting, it was necessary to change the current bit to a more ideal location.
   

Fix/Solution:
The FPGA bit, driveResetComplete, has been removed from the dedicatedIo Fault and Fault Mask registers. This bit has been replaced with driveBootComplete in the dedicatedIo Config register. This bit is monitored solely by the sqNodeLib utility. It is currently not visible through MPI calls or through Motion Console.
NOTE: This change causes compatibility issues between new FPGAs and old software (or old FPGAs with new software). FPGA version x0400 and later require the 03.04.00 MPI software release and later.


  The watchdog fault was incorrectly being cleared after being activated
    Reference Number: FP 465
    Type: Bug Fix
    FPGA Version: 0x0400
    Problem/Cause:
The Slice I/O watchdog fault was incorrectly being cleared after being activated. If a watchdog fault occurred, the FPGA would send a stop command to all slices to halt cyclic operation. As a result of being in this stop mode, it would cause the watchdog fault to be disabled and incorrectly clear itself. Therefore, the fault would never be seen.
   

Fix/Solution:
The FPGA was changed so that if the watchdog fault was the trigger to enter into the stop mode, the watchdog fault would not disable itself, thus allowing the fault to stay latched and also trigger the nodeIo fault.


  Support for a maximum count rate of 50MHz without filters
    Reference Number: FP 407
    Type: New Feature
    FPGA Version: 0x0400
   

Description:
The sqNode x0400 FPGA release introduces an upgraded network module, sqMac version 0300. Upgraded features include:

  • SynqNet HotReplace - allows one or more more nodes to be shutdown, replaced, and brought back on-line without interrupting other nodes.
  • Revised Cable Length Discovery - a new node-to-node method was added to make discovery more accurate.
  • sqPll shutdown - a controlled shutdown of individual nodes for HotReplace.

The sqMac 0300 version is NOT fully compatible with MPI versions prior to 03.04.00. Using 0300 sqMac with older software (for some configurations) might cause the "idle cable" check function to accidently corrupt normal packet traffic. But, the MPI will issue a warning if old/new FPGA/MPI are mixed by accident.


  Update the encoder word to 8-bits of multi-turn data and 24-bits of revolution data
    Reference Number: FP 405
    Type: General Change
    FPGA Version: 0x0400
    Problem/Cause:
For SFD feedback, the S200 drive supports 16 bits of multi-turn data and 24 bits of revolution data. In FPGA versions prior to x0400, the SynqNet FPGA C0FE0036 returned 16 bits of multi-turn data and the upper 16 bits of revolution data as the 32-bit SFD feedback word. This solution did not take advantage of the full resolution potential of the S200 drive.
   

Fix/Solution:
In FPGA version 0x0400 and later, the data returned as the 32-bit SFD feedback word is changed to the lower 8 bits of multi-turn data and all 24 bits of revolution data. This FPGA is being released with the 64-bit position feature of 03.04.00 MPI software release.

NOTE: By changing the resolution of the feedback word, tuning parameters will also need to change.


  Latch added on the notAmpPowered bit
    Reference Number: FP 402
    Type: General Change
    FPGA Version: 0x0400
    Problem/Cause:
In FPGA versions previous to 0x0400, the notAmpPowered fault bit was not latched.
   

Fix/Solution:
In FPGA versions 0x0400 and later, the notAmpPowered fault bit is now latched. If active, it can be cleared by writing a "1" to bit 5 of the dedicatedIo fault status register.


  Removal of adcGp module; addition of auxfb2_tb module
    Reference Number: FP 392
    Type: New Feature
    FPGA Version: 0x0400
    Description:
FPGA C0FE0036 version 0x0400 and later has many new features. New feedback types are now supported including SIN/COS, EnDat 2.1, and comcoder. These feedback sources are available for both primary and secondary feedback (SFD feedback is only available as primary feedback). Feedback sources are selected via "drive parameters" (MEIMotorEncoderTypeDrive is used in all cases). Hall input support has also be added.

NOTE: FPGA version 0x0400 and later require MPI software release 03.04.00 or later.


  Support for a maximum count rate of 50MHz without filters
    Reference Number: FP 337
    Type: New Feature
    FPGA Version: 0x0347; 0x0400
   

Description:
In FPGAs 0x0347, 0x0400, and later, the maximum quadrature encoder count rate has been improved to be 50MHz. In previous FPGA releases, the maximum count rate was 25MHz.

 

C0FE0036_0346_00_02

  Drive monitor A/B/C pointers corrupted on driveInterfaceParallelMaster
    Reference Number: FP 366
    Type: Bug Fix
    FPGA Version: 0x0346_00_02, 0x0347
    Problem/Cause:
Invalid data was returned from the Kollmorgen S200 drives in the MonitorA/B/C data fields. The data was invalid because the service channel write to the MonitorA/B/C pointer values failed. The writes failed because the Valid bit was omitted from the write decode logic; writes occurred when the valid bit was both on and off. This problem existed in all C0FE0036 versions prior to 0x0346_00_02.
   

Fix/Solution:
The FPGA code was corrected to use the Valid bit. This fix exists in FPGA versions 0x0346_00_02 and later. No software changes are required.

 

C0FE0036_0346_00_01

  Fix drive fault clear for driveInterfaceParallelMaster
    Reference Number: FP 360
    Type: Bug Fix
    FPGA Version: 0x0346_00_01, 0x0347
    Problem/Cause:
The DONE bit for the driveFaultClear direct command (in the service command handshake) was returned before the fault was actually cleared.
   

Fix/Solution:
The driveFault bit from the drive may take from 52.4ms to 104.9ms to clear. The FPGA was changed to hold off the DONE bit on this command for 105ms to allow for this variance.

 

C0FE0036_0346

  Modications to gpioPinConfigReg
    Reference Number: FP 336
    Type: General Change
    FPGA Version: 0x0346
    Problem/Cause:
Prior to FPGA version x0346, gpio pins that were configured as an "output" did not resume "output" direction after an ioAbort event. Also, during the ioAbort event, if a service channel write to the gpio configuration register occurred, the gpio "output" pins would be set to "output" mode momentarily (and then cleared to "input" mode by the ioAbort event). After the ioAbort event was cleared, the gpio pin state would remain as in "input" mode unless software restored the gpio configuration register again.
   

Fix/Solution:
In FPGA version x0346 and later, an ioAbort event still forces gpio "output" pins to "input" mode, which allows external resistors to pull pins from either high or low for a "safe" state. The resistors may or may not be present depending on the PCB assembly. However, during an ioAbort event, service writes to the gpio configuration register no longer cause momentary "output" direction. After the ioAbort event is cleared, gpio pins will resume their previous "output" state without software intervention.


  Intermittent Dual String Discovery Failure
    Reference Number: FP 332
    Type: Bug Fix
    FPGA Version: 0x0346
    Problem/Cause:
Probe, resetRequest, and resetComplete were repeated on the wrong port (OUT port) when using the OUT port as the primary port during SynqNet node discovery. As a result, SynqNet node discovery may have failed. This problem was caused by the probe, resetRequest, and resetComplete being repeated on the wrong port. This issue existed in all FPGA versions prior to x0346.
   

Fix/Solution:
The FPGA code was corrected in version x0346 and later releases. This fix is required for systems using the Dual String or IN Port String topologies. This fix is NOT required for systems using normal OUT Port String or Ring topologies.


  sqMac - 0x00 will be read for dataType NULL
    Reference Number: FP 323
    Type: New Feature
    FPGA Version: 0x0346
   

Description:
0x00 will be read for dataType NULL in the status and feedback packets.


  Intermittent Fault Recovery failures
    Reference Number: FP 315
    Type: Bug Fix
    FPGA Version: 0x0346
    Problem/Cause:
Some nodes may have intermittently failed to recover from a fault in some network configurations. If a node failed to recover, it exited cyclic operation and correctly triggered ioAbort logic (forcing outputs into "safe" states). Any nodes "downstream" of the failing node (after it switched ports) were also likely to exit cyclic operation. For any given node, there was only a small schedule window where this error may have occurred. There were two causes of the problem. The rcvMiiBuffer did not clear itself after an overflow in some situations. Also, a packet fragment generated by the fault recovery that happened to have valid CRC (but no data) would confuse the packetFifo, and corrupt internal node configuration bits. The first issue existed in FPGA build versions x0341 through x0345 and their branches (MPI release 03.02.00). The second issue existed in all FPGA versions prior to x0346.
   

Fix/Solution:
The fault recovery problems was corrected in FPGA build versions x0346 and later. The rcvMiiBuffer will correctly clear itself after an overflow. The xmitMiiReg will release xmitHoldRcvBuf within 8 clocks after a fault, preventing an rcvMiiBuffer overflow. 8 clocks will guarantee that there is minimum packet spacing between the packets. sqPll will ignore the second SYNQ packet after fault recovery (in case packet delays were effected in the cycle where fault recovery occurred). The rcvMii will correctly handle a valid packet with data length of 0. No software changes are required.


  Changed the pin location for gpio0_z[2] and number of gpioBits
    Reference Number: FP 307
    Type: General Change
    FPGA Version: 0x0346
   

Description:
Changed the pin location for gpio0_z[2] from T10 to G13. Changed the pin location for gpio0_z[13] from K5 to T10. Changed number of gpioBits from 13 to 14. This change applies to FPGA version x0346 and later.

 

C0FE0036_0344

  Block nodeAlarm to the drive if a driveFault is occurring
    Reference Number: FP 285
    Type: Bug Fix
    FPGA Version: 0x0344
   

Problem/Cause:
If nodeAlarm is configured to look at the axis fault, and the axis fault is configured to look at driveFault, a race condition would occur making both nodeAlarm and driveFault unclearable. This issue existed in all FPGA versions prior to x0344.

   

Fix/Solution:
Modified FPGA code for versions x0344 and later. If a driveFault is occurring, nodeAlarm is not written to the drive. This allows for both nodeAlarm and driveFault to be cleared. No software changes are required.

 

C0FE0036_0341

  sqMac rxMiiBuffer multiple packets
    Reference Number: FP 263
    Type: General Change
    FPGA Version: 0x0341
   

Description:
Add support for multiple packets to the rxMiiBuffer. This improves tolerance to network jitter. Prior to version x0341, the rxMiiBuffer could absorb up to 32 clocks (1.28 µS) of delay for a single packet, but only 8 clocks for multiple packets with minimum spacing. This change is required to meet theoretical worst-case network jitter in large networks (32 nodes). The improvement may also help at network startup, since the node's PLL phase error is larger than normal (as the PLL pulls into nominal lock). No software changes are required.


  New FPGA C0FE0036
    Reference Number: FP 243
    Type: General Change
    FPGA Version: 0x0341
   

Description:
Release new FPGA type C0FE0036_0341.sff.

 

C0FE0036_0340

  New BranchRev Register
    Reference Number: FP 231
    Type: New Feature
    FPGA Version: 0x0340
   

Description:
Add BranchRev register. This extends the existing 16 bits of FPGA version number with 8 bits of branch and 8 bits of revision ID.


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