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Release Note
C0FE0036_xxxx.sff

MPI Version
FPGA Version
03.03.00
Production Release
C0FE0036_0346_00_02
03.02.00
Production Release
C0FE0036_0344

  Table of Contents
     
    Changes and Bug Fixes
     

C0FE0036_0346_00_02
     Drive monitor A/B/C pointers corrupted on driveInterfaceParallelMaster - Bug Fix - FP366

C0FE0036_0346_00_01
     Fix drive fault clear for driveInterfaceParallelMaster - Bug Fix - FP360

C0FE0036_0346
     Modifications to gpioPinConfigReg - General Change - FP336
     Intermittent Dual String Discovery failure - Bug Fix - FP332
     sqMac - 0x00 will be read for dataType NULL - New Feature - FP323
     Intermittent Fault Recovery failures - Bug Fix - FP315
     Changed the pin location for gpio0_z[2] and number of gpioBits - General Change - FP307

C0FE0036_0344
     Block nodeAlarm to the drive if a driveFault is occurring - Bug Fix - FP285

C0FE0036_0341
     sqMac rxMiiBuffer multiple packets - General Change - FP263
     New FPGA C0FE0036 - General Change - FP243

C0FE0036_0340
     New BranchRev Register - New Feature - FP231


C0FE0036_0346_00_02

  Drive monitor A/B/C pointers corrupted on driveInterfaceParallelMaster
    Reference Number: FP 366
    Type: Bug Fix
    FPGA Version: 0x0346_00_02, 0x0347
    Problem/Cause:
Invalid data was returned from the Kollmorgen S200 drives in the MonitorA/B/C data fields. The data was invalid because the service channel write to the MonitorA/B/C pointer values failed. The writes failed because the Valid bit was omitted from the write decode logic; writes occurred when the valid bit was both on and off. This problem existed in all C0FE0036 versions prior to 0x0346_00_02.
   

Fix/Solution:
The FPGA code was corrected to use the Valid bit. This fix exists in FPGA versions 0x0346_00_02 and later. No software changes are required.

 

C0FE0036_0346_00_01

  Fix drive fault clear for driveInterfaceParallelMaster
    Reference Number: FP 360
    Type: Bug Fix
    FPGA Version: 0x0346_00_01, 0x0347
    Problem/Cause:
The DONE bit for the driveFaultClear direct command (in the service command handshake) was returned before the fault was actually cleared.
   

Fix/Solution:
The driveFault bit from the drive may take from 52.4ms to 104.9ms to clear. The FPGA was changed to hold off the DONE bit on this command for 105ms to allow for this variance.

 

C0FE0036_0346

  Modications to gpioPinConfigReg
    Reference Number: FP 336
    Type: General Change
    FPGA Version: 0x0346
    Problem/Cause:
Prior to FPGA version x0346, gpio pins that were configured as an "output" did not resume "output" direction after an ioAbort event. Also, during the ioAbort event, if a service channel write to the gpio configuration register occurred, the gpio "output" pins would be set to "output" mode momentarily (and then cleared to "input" mode by the ioAbort event). After the ioAbort event was cleared, the gpio pin state would remain as in "input" mode unless software restored the gpio configuration register again.
   

Fix/Solution:
In FPGA version x0346 and later, an ioAbort event still forces gpio "output" pins to "input" mode, which allows external resistors to pull pins from either high or low for a "safe" state. The resistors may or may not be present depending on the PCB assembly. However, during an ioAbort event, service writes to the gpio configuration register no longer cause momentary "output" direction. After the ioAbort event is cleared, gpio pins will resume their previous "output" state without software intervention.


  Intermittent Dual String Discovery Failure
    Reference Number: FP 332
    Type: Bug Fix
    FPGA Version: 0x0346
    Problem/Cause:
Probe, resetRequest, and resetComplete were repeated on the wrong port (OUT port) when using the OUT port as the primary port during SynqNet node discovery. As a result, SynqNet node discovery may have failed. This problem was caused by the probe, resetRequest, and resetComplete being repeated on the wrong port. This issue existed in all FPGA versions prior to x0346.
   

Fix/Solution:
The FPGA code was corrected in version x0346 and later releases. This fix is required for systems using the Dual String or IN Port String topologies. This fix is NOT required for systems using normal OUT Port String or Ring topologies.


  sqMac - 0x00 will be read for dataType NULL
    Reference Number: FP 323
    Type: New Feature
    FPGA Version: 0x0346
   

Description:
0x00 will be read for dataType NULL in the status and feedback packets.


  Intermittent Fault Recovery failures
    Reference Number: FP 315
    Type: Bug Fix
    FPGA Version: 0x0346
    Problem/Cause:
Some nodes may have intermittently failed to recover from a fault in some network configurations. If a node failed to recover, it exited cyclic operation and correctly triggered ioAbort logic (forcing outputs into "safe" states). Any nodes "downstream" of the failing node (after it switched ports) were also likely to exit cyclic operation. For any given node, there was only a small schedule window where this error may have occurred. There were two causes of the problem. The rcvMiiBuffer did not clear itself after an overflow in some situations. Also, a packet fragment generated by the fault recovery that happened to have valid CRC (but no data) would confuse the packetFifo, and corrupt internal node configuration bits. The first issue existed in FPGA build versions x0341 through x0345 and their branches (MPI release 03.02.00). The second issue existed in all FPGA versions prior to x0346.
   

Fix/Solution:
The fault recovery problems was corrected in FPGA build versions x0346 and later. The rcvMiiBuffer will correctly clear itself after an overflow. The xmitMiiReg will release xmitHoldRcvBuf within 8 clocks after a fault, preventing an rcvMiiBuffer overflow. 8 clocks will guarantee that there is minimum packet spacing between the packets. sqPll will ignore the second SYNQ packet after fault recovery (in case packet delays were effected in the cycle where fault recovery occurred). The rcvMii will correctly handle a valid packet with data length of 0. No software changes are required.


  Changed the pin location for gpio0_z[2] and number of gpioBits
    Reference Number: FP 307
    Type: General Change
    FPGA Version: 0x0346
   

Description:
Changed the pin location for gpio0_z[2] from T10 to G13. Changed the pin location for gpio0_z[13] from K5 to T10. Changed number of gpioBits from 13 to 14. This change applies to FPGA version x0346 and later.

 

C0FE0036_0344

  Block nodeAlarm to the drive if a driveFault is occurring
    Reference Number: FP 285
    Type: Bug Fix
    FPGA Version: 0x0344
   

Problem/Cause:
If nodeAlarm is configured to look at the axis fault, and the axis fault is configured to look at driveFault, a race condition would occur making both nodeAlarm and driveFault unclearable. This issue existed in all FPGA versions prior to x0344.

   

Fix/Solution:
Modified FPGA code for versions x0344 and later. If a driveFault is occurring, nodeAlarm is not written to the drive. This allows for both nodeAlarm and driveFault to be cleared. No software changes are required.

 

C0FE0036_0341

  sqMac rxMiiBuffer multiple packets
    Reference Number: FP 263
    Type: General Change
    FPGA Version: 0x0341
   

Description:
Add support for multiple packets to the rxMiiBuffer. This improves tolerance to network jitter. Prior to version x0341, the rxMiiBuffer could absorb up to 32 clocks (1.28 µS) of delay for a single packet, but only 8 clocks for multiple packets with minimum spacing. This change is required to meet theoretical worst-case network jitter in large networks (32 nodes). The improvement may also help at network startup, since the node's PLL phase error is larger than normal (as the PLL pulls into nominal lock). No software changes are required.


  New FPGA C0FE0036
    Reference Number: FP 243
    Type: General Change
    FPGA Version: 0x0341
   

Description:
Release new FPGA type C0FE0036_0341.sff.

 

C0FE0036_0340

  New BranchRev Register
    Reference Number: FP 231
    Type: New Feature
    FPGA Version: 0x0340
   

Description:
Add BranchRev register. This extends the existing 16 bits of FPGA version number with 8 bits of branch and 8 bits of revision ID.


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