Release Note
C0FE0030_xxxx.sff
MPI Version |
FPGA Version |
03.03.00
Production Release |
C0FE0030_0346 |
03.02.00
Production Release |
C0FE0030_0342 |
C0FE0030_0346
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Intermittent Dual String Discovery Failure |
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Reference Number: FP 332 |
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Type: Bug Fix |
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FPGA Version: 0x0346 |
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Problem/Cause:
Probe, resetRequest, and resetComplete were repeated on the wrong port (OUT port) when using the OUT port as the primary port during SynqNet node discovery. As a result, SynqNet node discovery may have failed. This problem was caused by the probe, resetRequest, and resetComplete being repeated on the wrong port. This issue existed in all FPGA versions prior to x0346. |
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Fix/Solution:
The FPGA code was corrected in version x0346 and later releases. This fix is required for systems using the Dual String or IN Port String topologies. This fix is NOT required for systems using normal OUT Port String or Ring topologies.
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sqMac - 0x00 will be read for dataType NULL |
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Reference Number: FP 323 |
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Type: New Feature |
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FPGA Version: 0x0346 |
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Description:
0x00 will be read for dataType NULL in the status and feedback packets.
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Intermittent Fault Recovery failures |
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Reference Number: FP 315 |
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Type: Bug Fix |
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FPGA Version: 0x0346 |
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Problem/Cause:
Some nodes may have intermittently failed to recover from a fault in some network configurations. If a node failed to recover, it exited cyclic operation and correctly triggered ioAbort logic (forcing outputs into "safe" states). Any nodes "downstream" of the failing node (after it switched ports) were also likely to exit cyclic operation. For any given node, there was only a small schedule window where this error may have occurred. There were two causes of the problem. The rcvMiiBuffer did not clear itself after an overflow in some situations. Also, a packet fragment generated by the fault recovery that happened to have valid CRC (but no data) would confuse the packetFifo, and corrupt internal node configuration bits. The first issue existed in FPGA build versions x0341 through x0345 and their branches (MPI release 03.02.00). The second issue existed in all FPGA versions prior to x0346. |
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Fix/Solution:
The fault recovery problems have been fixed in FPGA build versions x0346 and later. The rcvMiiBuffer will correctly clear itself after an overflow. The xmitMiiReg will release xmitHoldRcvBuf within 8 clocks after a fault, preventing an rcvMiiBuffer overflow. 8 clocks will guarantee that there is minimum packet spacing between the packets. sqPll will ignore the second SYNQ packet after fault recovery (in case packet delays were effected in the cycle where fault recovery occurred). The rcvMii will correctly handle a valid packet with data length of 0. No software changes are required.
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nodeIoSpi - State machine hangs during an SPI cycle |
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Reference Number: FP 290 |
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Type: Bug Fix |
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FPGA Version: 0x0346 |
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Problem/Cause:
NodeIo digital inputs or analog inputs may have stopped updating in certain situations. If the start bits were enabled during a SPI cycle, the receive state machine would hang. This problem occurred because at the beginning of the cycle, the start bits were not enabled. Therefore, the transmit engine did not send the start bits. By the end of the cycle, the start bits were enabled, causing the receive engine to wait for the bits to arrive. As a result, the receive engine was stuck in this wait state. This issue existed prior to FPGA release x0346. |
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Fix/Solution:
The FPGA design has been fixed in FPGA release x0346 and later.
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C0FE0030_0342
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nodeIoSpi transmit buffer clock |
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Reference Number: FP 269 |
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Type: Bug Fix |
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FPGA Version: 0x0342 |
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Problem/Cause:
C0FE0030 SPI bus transmit data may be corrupted. The dual port buffer logic was running on 25 MHz clock instead of 50 MHz clock. This problem only exists in version x0341.
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Problem/Cause:
FPGA code was corrected to use 50 MHz clock. This fix is in version x0342 and later. No software changes are required.
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C0FE0030_0341
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sqMac rxMiiBuffer multiple packets |
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Reference Number: FP 263 |
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Type: General Change |
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FPGA Version: 0x0341 |
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Description:
Add support for multiple packets to the rxMiiBuffer. This improves tolerance to network jitter. Prior to version x0341, the rxMiiBuffer could absorb up to 32 clocks (1.28 µS) of delay for a single packet, but only 8 clocks for multiple packets with minimum spacing. This change is required to meet theoretical worst-case network jitter in large networks (32 nodes). The improvement may also help at network startup, since the node's PLL phase error is larger than normal (as the PLL pulls into nominal lock). No software changes are required.
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nodeIoSpi 12.5MHz SPI bus |
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Reference Number: FP 245 |
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Type: General Change |
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FPGA Version: 0x0341 |
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Problem/Cause:
The nodeIoSpi module does not work correctly when configured for a 12.5 MHz SPI bus clock rate.
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Fix/Solution:
The FPGA code was modifed to use a 50 MHz clock rate in the nodeIoSpi module, allowing 12.5 MHz SPI bus clock rate in FPGA versions x0341 and later. No software changes are required.
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C0FE0030_0340
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New BranchRev Register |
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Reference Number: FP 231 |
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Type: New Feature |
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FPGA Version: 0x0340 |
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Description:
Add BranchRev register. This extends the existing 16 bits of FPGA version number with 8 bits of branch and 8 bits of revision ID.
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