.

Release Note
C0FE0014_xxxx.sff

MPI Version
FPGA Version
03.03.00
Production Release
C0FE0014_0346.sff
03.02.00
Production Release
C0FE0014_0341.sff
03.01.01
C0FE0014_0320.sff
03.01.00
Production Release
C0FE0014_0311.sff

  Table of Contents
     
    Changes and Bug Fixes
     

C0FE0014_0346
     Modifications to gpioPinConfigReg - General Change - FP336
     Intermittent Dual String Discovery failure - Bug Fix - FP332
     sqMac - 0x00 will be read for dataType NULL - New Feature - FP323
     Intermittent Fault Recovery failures - Bug Fix - FP315
     Support for big and little endian byte ordering - New Feature - FP301

C0FE0014_0341
     sqMac rxMiiBuffer multiple packets - General Change - FP263

C0FE0014_0340
     New BranchRev Register - New Feature - FP231

C0FE0014_0320
     sqNode driveMemory clock domain fix - Bug Fix - FP212

C0FE0014_0311
     Expansion of dedicatedIo to 32 bits - General Change - FP167
     Clearing driveWatchdogFault and the driveChecksumError - Bug Fix - FP160
     Set unused pin default to FLOAT - General Change - FP155

C0FE0014_0303
     SqMac Cyclic Status - Bug Fix - FP141
     Support for Multi-Vendor Flash Download - General Change - FP140
     NodeDisable and analogPowerFault invert - Bug Fix - FP139
     PhaseAdjust clash - Bug Fix - FP137
     24mA drive for GPIO pins - General Change - FP134
     SqMax rcvDataUnload - Bug Fix - FP123
     Improved Secondary Encoder Support - General Change - FP109
     Improved ADC Support - General Change -FP108


C0FE0014_0346

  Modications to gpioPinConfigReg
    Reference Number: FP 336
    Type: General Change
    FPGA Version: 0x0346
    Problem/Cause:
Prior to FPGA version x0346, gpio pins that were configured as an "output" did not resume "output" direction after an ioAbort event. Also, during the ioAbort event, if a service channel write to the gpio configuration register occurred, the gpio "output" pins would be set to "output" mode momentarily (and then cleared to "input" mode by the ioAbort event). After the ioAbort event was cleared, the gpio pin state would remain as in "input" mode unless software restored the gpio configuration register again.
   

Fix/Solution:
In FPGA version x0346 and later, an ioAbort event still forces gpio "output" pins to "input" mode, which allows external resistors to pull pins from either high or low for a "safe" state. The resistors may or may not be present depending on the PCB assembly. However, during an ioAbort event, service writes to the gpio configuration register no longer cause momentary "output" direction. After the ioAbort event is cleared, gpio pins will resume their previous "output" state without software intervention.


  Intermittent Dual String Discovery Failure
    Reference Number: FP 332
    Type: Bug Fix
    FPGA Version: 0x0346
    Problem/Cause:
Probe, resetRequest, and resetComplete were repeated on the wrong port (OUT port) when using the OUT port as the primary port during SynqNet node discovery. As a result, SynqNet node discovery may have failed. This problem was caused by the probe, resetRequest, and resetComplete being repeated on the wrong port. This issue existed in all FPGA versions prior to x0346.
   

Fix/Solution:
The FPGA code was corrected in version x0346 and later releases. This fix is required for systems using the Dual String or IN Port String topologies. This fix is NOT required for systems using normal OUT Port String or Ring topologies.


  sqMac - 0x00 will be read for dataType NULL
    Reference Number: FP 323
    Type: New Feature
    FPGA Version: 0x0346
   

Description:
0x00 will be read for dataType NULL in the status and feedback packets.


  Intermittent Fault Recovery failures
    Reference Number: FP 315
    Type: Bug Fix
    FPGA Version: 0x0346
    Problem/Cause:
Some nodes may have intermittently failed to recover from a fault in some network configurations. If a node failed to recover, it exited cyclic operation and correctly triggered ioAbort logic (forcing outputs into "safe" states). Any nodes "downstream" of the failing node (after it switched ports) were also likely to exit cyclic operation. For any given node, there was only a small schedule window where this error may have occurred. There were two causes of the problem. The rcvMiiBuffer did not clear itself after an overflow in some situations. Also, a packet fragment generated by the fault recovery that happened to have valid CRC (but no data) would confuse the packetFifo, and corrupt internal node configuration bits. The first issue existed in FPGA build versions x0341 through x0345 and their branches (MPI release 03.02.00). The second issue existed in all FPGA versions prior to x0346.
   

Fix/Solution:
The fault recovery problems was corrected in FPGA build versions x0346 and later. The rcvMiiBuffer will correctly clear itself after an overflow. The xmitMiiReg will release xmitHoldRcvBuf within 8 clocks after a fault, preventing an rcvMiiBuffer overflow. 8 clocks will guarantee that there is minimum packet spacing between the packets. sqPll will ignore the second SYNQ packet after fault recovery (in case packet delays were effected in the cycle where fault recovery occurred). The rcvMii will correctly handle a valid packet with data length of 0. No software changes are required.


  Support for big and little endian bytes
    Reference Number: FP 301
    Type: New Feature
    FPGA Version: 0x0346
   

Description:
Support has been added for big endian or little endian byte ordering in the driveParallel interface.



C0FE0014_0341

  sqMac rxMiiBuffer multiple packets
    Reference Number: FP 263
    Type: General Change
    FPGA Version: 0x0341
   

Description:
Add support for multiple packets to the rxMiiBuffer. This improves tolerance to network jitter. Prior to version x0341, the rxMiiBuffer could absorb up to 32 clocks (1.28 µS) of delay for a single packet, but only 8 clocks for multiple packets with minimum spacing. This change is required to meet theoretical worst-case network jitter in large networks (32 nodes). The improvement may also help at network startup, since the node's PLL phase error is larger than normal (as the PLL pulls into nominal lock). No software changes are required.

 

C0FE0014_0340

  New BranchRev Register
    Reference Number: FP 231
    Type: New Feature
    FPGA Version: 0x0340
   

Description:
Add BranchRev register. This extends the existing 16 bits of FPGA version number with 8 bits of branch and 8 bits of revision ID.

 

C0FE0014_0320

  sqNode driveMemory clock domain fix
    Reference Number: FP 212
    Type: Bug Fix
    FPGA Version: 0x0320
   

Problem/Cause:
Service channel data sent to or from a drive, may have been corrupted. This was caused by an FPGA bug in crossing clock domains from driveClk to the internal 25 MHz clock. This problem could have occurred in any driveParallel designs (C0FE0014, C0FE0019, C0FE0031) prior to version 0x0320.

   

Fix/Solution:
The FPGA code was modified to prevent clock domain problems. This problem was fixed in FPGA versions 0x0320 and later.

 

C0FE0014_0311

  dedicatedIo - Expansion of dedicatedIn to 32 bits
    Reference Number: FP 167
    Type: General Change
    FPGA Version: 0x0311
   

Description:
Expand the dedicatedIn word from 16 bits to 32 bits and add the status bits Feedback 0 Fault and Feedback 1 Fault. Note: Although the FPGAs now supports additional bits, the MPI does not yet enable them.


  Clearing driveWatchdogFault and driveChecksumError
    Reference Number: FP 160
    Type: Bug Fix
    FPGA Version: 0x0311
   

Problem/Cause:
Clearing the driveWatchdogFault and driveChecksumError required two service comands—a write to start the clear, and a write to end the clear. MPI releases prior to the 03.01.00 did not clear the bits.

   

Fix/Solution:
Corrected the Drive Watchdog Fault and Drive Checksum Error bits to clear with a single service command. MPI releases 03.01.00 and later support this new behavior and clear the bits after a network reset.


  Set unused pin default to FLOAT
    Reference Number: FP 155
    Type: General Change
    FPGA Version: 0x0311
   

Description:
Set unused pins to FLOAT after the FPGA configuration process. After a power-on, but prior to FPGA configuration, SynqNet FPGA pins should be high-impedance outputs.

NOTE: The mode pins can enable internal pullups, but this is not recommended for SynqNet.

After configuration, unused pins will be high-impedance outputs with no internal pull-up or pulldown. In earlier versions, unused pins would default to weak internal pulldowns. This was not ideal since it could have conflicted with an external pull-up.


C0FE0014_0303

  SqMax Cyclic Status
    Reference Number: FP 141
    Type: Bug Fix
    FPGA Version: 0x0303
   

Problem/Cause:
There was a problem where SqMax NodeStatus cyclic status bits may have been corrupted after reading some of the FPGA registers (via the service command). The bits that could have been corrupted are: analogPowerFault, ioAbort, nodeAlarm, and nodeDisable. This issue has existed since release x0100.

   

Fix/Solution:
This problem has been fixed.


  Support for Multi-Vendor Flash Download
    Reference Number: FP 140
    Type: General Change
    FPGA Version: 0x0303
   

Description:
Support has been added for a number of different flash component vendors. Flash components that are currently supported are:

Vendor
PN
Size
Circuit
Atmel
AT25F2048N-10SI-2.7 (2MB)
2MB
Bowsprit
Atmel
AT45DB021B
2MB
Bowsprit
Atmel
AT45DB041B
4MB
Bowsprit
Atmel
AT45DB081B
8MB
Bowsprit
NEXFLASH
NX25P20-VN
2MB
Bowsprit
NEXFLASH
NX25P40-VN
4MB
Bowsprit
SST
SST25VF020-20-4C-SA
2MB
Bowsprit
SST
SST25VF040-20-4C-SA
4MB
Bowsprit
STM
M25P20-VMN6T
2MB
Bowsprit
STM
M25P40-VMN6T
4MB
Bowsprit
STM
M25P80-VMN6T
8MB
Bowsprit
Xilinx
XC18V02
2MB
Outrigger

  NodeDisable and analogPowerFault invert
    Reference Number: FP 139
    Type: Bug Fix
    FPGA Version: 0x0303
   

Problem/Cause:
There was a problem with the inverted polarity option for the FPGA inputs nodeDisable and analogPowerFault. Prior to this fix, only the default polarity was functional. The problem happened because the hardware invert logic was inserted after the hardware latch function. Therefore, when "invert" was selected, the input would typically latch the negated state, and would not report a fault unless the latch was cleared by a software command. If the "invert" option was NOT used, the input would function correctly. This issue did not exist until the x020C release, where these inputs were first latched.

   

Fix/Solution:
This problem has been fixed.


  PhaseAdjust clash
    Reference Number: FP 137
    Type: Bug Fix
    FPGA Version: 0x0303
   

Problem/Cause:
There was a problem in the sqPll function of the sqMac. With certain timing values, one node in the network may have fail to hold lock and then aborts cyclic operation. For a typical 3-node network, this timing typically occurred with TxTime set to 95%. Other TxTime values may fail in other network configurations.

   

Fix/Solution:
This problem has been fixed.


  24mA drive for GPIO pins
    Reference Number: FP 134
    Type: General Change
    FPGA Version: 0x0303
   

Description:
The drive current of GPIO pins has been increased to +/-24mA. Other outputs which may drive opto isolators (LED outputs, nodeAlarm, ampEnable, brakeApplied) were already configured for 24mA drive current. See individual FPGA specifications for complete details of I/O characteristics.


  SqMax rcvDataUnload
    Reference Number: FP 123
    Type: Bug Fix
    FPGA Version: 0x0303
   

Problem/Cause:
There was a problem in the receive data unload function of the sqMax. In certain situations where the packet size did not match the configured packet size, invalid sqMax outputs were observed to cause "glitches" in the I/O output signals. The glitches would occur at the transition from cyclic to asynq operation, but the ioAbort signal would normally prevent these glitches from reaching external logic.

   

Fix/Solution:
This problem has been fixed.


  Improved Secondary Encoder Support
    Reference Number: FP 109
    Type: General Change
    FPGA Version: 0x0303
   

Description:
Improvements have been made to the secondary encoder features. These changes allow the use of encoder faults and capture with secondary encoders. Secondary feedback for drives has also been added. The changes are NOT backwards compatible with software releases prior to 20031222 (secondary encoder feedback is not fully functional with prior software).


  Improved ADC Support
    Reference Number: FP 108
    Type: General Change
    FPGA Version: 0x0303
   

Description:
Improvements have been made to the ADC features to use the new "nodeIo" conventions. These changes allow up to 8 ADC channels per node (prior to this, the default was 1 ADC channel per motor). The changes are NOT backwards compatible with software releases prior to 20031222 (ADCs are not functional with prior software).

 

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