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Release Note
C0FE0030_xxxx.sff

MPI Version
FPGA Version
03.02.00
Production Release
C0FE0030_0342

  Table of Contents
     
    Changes and Bug Fixes
     

C0FE0030_0342
     nodeIoSpi transmit buffer clock - Bug Fix - FP269

C0FE0030_0341
     sqMac rxMiiBuffer multiple packets - General Change - FP263
     nodeIoSpi 12.5MHz SPI bus - General Change - FP245

C0FE0030_0340
     New BranchRev Register - New Feature - FP231


C0FE0030_0342

  nodeIoSpi transmit buffer clock
    Reference Number: FP 269
    Type: Bug Fix
    FPGA Version: 0x0342
   

Problem/Cause:
C0FE0030 SPI bus transmit data may be corrupted. The dual port buffer logic was running on 25 MHz clock instead of 50 MHz clock. This problem only exists in version x0341.

   

Problem/Cause:
FPGA code was corrected to use 50 MHz clock. This fix is in version x0342 and later. No software changes are required.

 

C0FE0030_0341

  sqMac rxMiiBuffer multiple packets
    Reference Number: FP 263
    Type: General Change
    FPGA Version: 0x0341
   

Description:
Add support for multiple packets to the rxMiiBuffer. This improves tolerance to network jitter. Prior to version x0341, the rxMiiBuffer could absorb up to 32 clocks (1.28 µS) of delay for a single packet, but only 8 clocks for multiple packets with minimum spacing. This change is required to meet theoretical worst-case network jitter in large networks (32 nodes). The improvement may also help at network startup, since the node's PLL phase error is larger than normal (as the PLL pulls into nominal lock). No software changes are required.


  nodeIoSpi 12.5MHz SPI bus
    Reference Number: FP 245
    Type: General Change
    FPGA Version: 0x0341
   

Problem/Cause:
The nodeIoSpi module does not work correctly when configured for a 12.5 MHz SPI bus clock rate.

   

Fix/Solution:
The FPGA code was modifed to use a 50 MHz clock rate in the nodeIoSpi module, allowing 12.5 MHz SPI bus clock rate in FPGA versions x0341 and later. No software changes are required.

 

C0FE0030_0340

  New BranchRev Register
    Reference Number: FP 231
    Type: New Feature
    FPGA Version: 0x0340
   

Description:
Add BranchRev register. This extends the existing 16 bits of FPGA version number with 8 bits of branch and 8 bits of revision ID.

 

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