.

Release Note
C0FE0029_xxxx.sff

MPI Version
FPGA Version
03.02.00
Production Release
C0FE0029_0345
03.01.01
C0FE0029_0311
03.01.00
Production Release
C0FE0029_0311

  Table of Contents
     
    Changes and Bug Fixes
     

C0FE0029_0345
     Pulse count sample problem with missed packets - Bug Fix - FP291

C0FE0029_0340
     New BranchRev Register - New Feature - FP231

C0FE0029_0341
     sqMac rxMiiBuffer multiple packets - General Change - FP263
     sqNode adcAd977 double buffer - General Change - FP260

C0FE0029_0311
     sqNode C0FE0029: removal of compare features - General Change - FP175
     Expansion of dedicatedIo to 32 bits - General Change - FP167
     Clearing driveWatchdogFault and the driveChecksumError - Bug Fix - FP160
     Set unused pin default to FLOAT - General Change - FP155

C0FE0029_0303
     SqMac Cyclic Status - Bug Fix - FP141
     Support for Multi-Vendor Flash Download - General Change - FP140
     NodeDisable and analogPowerFault invert - Bug Fix - FP139
     PhaseAdjust clash - Bug Fix - FP137
     24mA drive for GPIO pins - General Change - FP134
     SqMax rcvDataUnload - Bug Fix - FP123
     Improved Secondary Encoder Support - General Change - FP109
     Improved ADC Support - General Change -FP108


C0FE0029_0345

  Pulse count sample problem with missed packets
    Reference Number: FP 291
    Type: Bug Fix
    FPGA Version: 0x0345
   

Problem/Cause:
The pulse engine (step/direction logic) may appear to have a momentary position error after network packet errors (or fault recovery). The FPGA pulseFeedback value was not updated when DEMAND packet errors occurred. The "old" pulseFeedback value was sent back to the controller until valid DEMAND packets arrived, which may look like zero velocity to the controller. If a fault recovery is in progress, and the controller does not receive the FEEDBACK packet, the controller will interpolate the expected position based on constant velocity, then at the end of recovery, the controller may get one FEEDBACK packet with "old" pulseFeedback position (correct pulseFeedback will arrive in subsequent packets). This issue existed in all FPGAs prior to version x0345.

   

Fix/Solution:
The FPGA code was corrected in versions x0345 and later. No software changes are required.

 

C0FE0029_0340

  New BranchRev Register
    Reference Number: FP 231
    Type: New Feature
    FPGA Version: 0x0340
   

Description:
Add BranchRev register. This extends the existing 16 bits of FPGA version number with 8 bits of branch and 8 bits of revision ID.

 

C0FE0029_0341

  sqMac rxMiiBuffer multiple packets
    Reference Number: FP 263
    Type: General Change
    FPGA Version: 0x0341
   

Description:
Add support for multiple packets to the rxMiiBuffer. This improves tolerance to network jitter. Prior to version x0341, the rxMiiBuffer could absorb up to 32 clocks (1.28 µS) of delay for a single packet, but only 8 clocks for multiple packets with minimum spacing. This change is required to meet theoretical worst-case network jitter in large networks (32 nodes). The improvement may also help at network startup, since the node's PLL phase error is larger than normal (as the PLL pulls into nominal lock). No software changes are required.


  sqNode adcAd977 double buffer
    Reference Number: FP 260
    Type: General Change
    FPGA Version: 0x0341
   

Description:
Add double-buffering to the ADC input data. This change eliminates the need for a SynqNet scheduling limit (and the corresponding software error check). Prior to version x0341, a software error check prevented operation if the controller cycle time was less than the time required to complete the full ADC read sequence of all enabled channels. Otherwise, there would be a chance that packet data might be sent while new ADC data was arriving. This might result in some data from the "new" ADC read, and some data from the "old" (previous) read. If one 16-bit ADC value contained 8 bits of "old" and 8 bits of "new" data, this could cause an invalid value. For version x0341 and later, the ADC read data is double-buffered to prevent the possibility of bad data. If the controller cycle is faster than the ADC cycle, the node will send "old" data in multiple packets while the ADC cycle completes, then switch to "new" data.

NOTE: For existing systems, with controller cycles longer than ADC cycles, there is no change in ADC behavior. However, for new systems (with new MPI releases) it is possible to use higher controller rates without reducing the number of enabled ADC channels.

New FPGAs (x0341 and later) are fully backwards compatible with old MPI software releases. New MPI releases (starting with 03.02.xx) are generally compatible with old FPGAs (prior to version x0341). However, the former error check for ADC cycle period has been eliminated, so it is possible to configure a controller cycle rate fast enough to cause a problem when using old FPGAs with new MPI.

 

C0FE0029_0311

  sqNode C0FE0029: removal of compare features
    Reference Number: FP 175
    Type: General Change
    FPGA Version: 0x0311
   

Description:
C0FE0029 no longer supports compare. This feature was deleted due to lack of FPGA space.

NOTE: The MPI does not yet support compare, so this does not affect existing systems.


  dedicatedIo - Expansion of dedicatedIn to 32 bits
    Reference Number: FP 167
    Type: General Change
    FPGA Version: 0x0311
   

Description:
Expand the dedicatedIn word from 16 bits to 32 bits and add the status bits Feedback 0 Fault and Feedback 1 Fault. Note: Although the FPGAs now supports additional bits, the MPI does not yet enable them.


  Clearing driveWatchdogFault and driveChecksumError
    Reference Number: FP 160
    Type: Bug Fix
    FPGA Version: 0x0311
   

Problem/Cause:
Clearing the driveWatchdogFault and driveChecksumError required two service comands—a write to start the clear, and a write to end the clear. MPI releases prior to the 03.01.00 did not clear the bits.

   

Fix/Solution:
Corrected the Drive Watchdog Fault and Drive Checksum Error bits to clear with a single service command. MPI releases 03.01.00 and later support this new behavior and clear the bits after a network reset.


  Set unused pin default to FLOAT
    Reference Number: FP 155
    Type: General Change
    FPGA Version: 0x0311
   

Description:
Set unused pins to FLOAT after the FPGA configuration process. After a power-on, but prior to FPGA configuration, SynqNet FPGA pins should be high-impedance outputs.

NOTE: The mode pins can enable internal pullups, but this is not recommended for SynqNet.

After configuration, unused pins will be high-impedance outputs with no internal pull-up or pulldown. In earlier versions, unused pins would default to weak internal pulldowns. This was not ideal since it could have conflicted with an external pull-up.

 

C0FE0029_0303

  SqMax Cyclic Status
    Reference Number: FP 141
    Type: Bug Fix
    FPGA Version: 0x0303
   

Problem/Cause:
There was a problem where SqMax NodeStatus cyclic status bits may have been corrupted after reading some of the FPGA registers (via the service command). The bits that could have been corrupted are: analogPowerFault, ioAbort, nodeAlarm, and nodeDisable. This issue has existed since release x0100.

   

Fix/Solution:
This problem has been fixed.


  Support for Multi-Vendor Flash Download
    Reference Number: FP 140
    Type: General Change
    FPGA Version: 0x0303
   

Description:
Support has been added for a number of different flash component vendors. Flash components that are currently supported are:

Vendor
PN
Size
Circuit
Atmel
AT25F2048N-10SI-2.7 (2MB)
2MB
Bowsprit
Atmel
AT45DB021B
2MB
Bowsprit
Atmel
AT45DB041B
4MB
Bowsprit
Atmel
AT45DB081B
8MB
Bowsprit
NEXFLASH
NX25P20-VN
2MB
Bowsprit
NEXFLASH
NX25P40-VN
4MB
Bowsprit
SST
SST25VF020-20-4C-SA
2MB
Bowsprit
SST
SST25VF040-20-4C-SA
4MB
Bowsprit
STM
M25P20-VMN6T
2MB
Bowsprit
STM
M25P40-VMN6T
4MB
Bowsprit
STM
M25P80-VMN6T
8MB
Bowsprit
Xilinx
XC18V02
2MB
Outrigger

  NodeDisable and analogPowerFault invert
    Reference Number: FP 139
    Type: Bug Fix
    FPGA Version: 0x0303
   

Problem/Cause:
There was a problem with the inverted polarity option for the FPGA inputs nodeDisable and analogPowerFault. Prior to this fix, only the default polarity was functional. The problem happened because the hardware invert logic was inserted after the hardware latch function. Therefore, when "invert" was selected, the input would typically latch the negated state, and would not report a fault unless the latch was cleared by a software command. If the "invert" option was NOT used, the input would function correctly. This issue did not exist until the x020C release, where these inputs were first latched.

   

Fix/Solution:
This problem has been fixed.


  PhaseAdjust clash
    Reference Number: FP 137
    Type: Bug Fix
    FPGA Version: 0x0303
   

Problem/Cause:
There was a problem in the sqPll function of the sqMac. With certain timing values, one node in the network may have fail to hold lock and then aborts cyclic operation. For a typical 3-node network, this timing typically occurred with TxTime set to 95%. Other TxTime values may fail in other network configurations.

   

Fix/Solution:
This problem has been fixed.


  24mA drive for GPIO pins
    Reference Number: FP 134
    Type: General Change
    FPGA Version: 0x0303
   

Description:
The drive current of GPIO pins has been increased to +/-24mA. Other outputs which may drive opto isolators (LED outputs, nodeAlarm, ampEnable, brakeApplied) were already configured for 24mA drive current. See individual FPGA specifications for complete details of I/O characteristics.


  SqMax rcvDataUnload
    Reference Number: FP 123
    Type: Bug Fix
    FPGA Version: 0x0303
   

Problem/Cause:
There was a problem in the receive data unload function of the sqMax. In certain situations where the packet size did not match the configured packet size, invalid sqMax outputs were observed to cause "glitches" in the I/O output signals. The glitches would occur at the transition from cyclic to asynq operation, but the ioAbort signal would normally prevent these glitches from reaching external logic.

   

Fix/Solution:
This problem has been fixed.


  Improved Secondary Encoder Support
    Reference Number: FP 109
    Type: General Change
    FPGA Version: 0x0303
   

Description:
Improvements have been made to the secondary encoder features. These changes allow the use of encoder faults and capture with secondary encoders. Secondary feedback for drives has also been added. The changes are NOT backwards compatible with software releases prior to 20031222 (secondary encoder feedback is not fully functional with prior software).


  Improved ADC Support
    Reference Number: FP 108
    Type: General Change
    FPGA Version: 0x0303
   

Description:
Improvements have been made to the ADC features to use the new "nodeIo" conventions. These changes allow up to 8 ADC channels per node (prior to this, the default was 1 ADC channel per motor). The changes are NOT backwards compatible with software releases prior to 20031222 (ADCs are not functional with prior software).

 

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