Description

The sqMac module (the network interface logic) was upgraded to support up to 64 nodes. Key changes include:

larger packet forwarding buffer. Previously 128 bits deep, now 2048 bits (Spartan2/2e) or 8196 bits (Spartan3/3e).

Improved support for pipelined service commands.

A new unified Capture module was created to replace the older versions of both the Capture and Probe modules. In addition, new trigger features were introduced.

All Capture modules have a base feature set: Single-shot capture with the new trigger select, pre-trigger condition, and filter options. This Single-shot capture replaces the basic capture in prior FPGA versions. Some FPGAs support an additional Auto-arm mode. When enabled by software, Auto-arm uses a capture buffer memory to store multiple capture events (replaces the Probe module in prior FPGA versions).

The new trigger logic is common to all FPGAs (and slightly different to prior FPGA versions). Up to 32 trigger source inputs are available. The exact set of trigger source signals depends on the IO for each node. A trigger event can be selected from any input, with rising, falling, or both edges active. An optional filter function can be used to deglitch the signal. An optional pre-condition (based on the same trigger sources) can be specified: pre-condition high, low, rising edge, falling edge, or both.

For more information about using the new capture features, see Capture Objects.

Problem/Cause:

The driveClkInvert cannot be read back by service command. Writes work correctly, however the read value is always 0.

This bit was added to the driveInterfaceSerial module in sqNode Build 0400_03_02. However, the read path was missing from the FPGA source code.

Fix/Solution:
The FPGA logic was corrected.

Description:

This feature is only relavant to drives that require clock inversion to set the correct boot source. For example drives that use TMS320F2801 as listed below.

The drive serial interface has a clock output which is low when clocks are not being emitted.
Unfortunately on the TMS320F2801 processor, the SPI clock input pin is also a boot control pin and for the DSP to boot normally this pin must be high. To permit this a further bit was added to the clkCfg register (bit 5) which inverts the driveClk output.

Kollmorgen MSM4 C0FE0043
Kollmorgen NIM-MSM1-V2 C0FE0045
Kollmorgen NIM-MSM1-V3 C0FE0045
Kollmorgen NIM-V2 C0FE0045
Kollmorgen NIM-V3 C0FE0045
Kollmorgen NIM-LAM2-V2 C0FE0045
Kollmorgen NIM-LAM2-V3 C0FE0045