Description

The sqMac module (the network interface logic) was upgraded to support up to 64 nodes. Key changes include:

larger packet forwarding buffer. Previously 128 bits deep, now 2048 bits (Spartan2/2e) or 8196 bits (Spartan3/3e).

Improved support for pipelined service commands.

A new unified Capture module was created to replace the older versions of both the Capture and Probe modules. In addition, new trigger features were introduced.

All Capture modules have a base feature set: Single-shot capture with the new trigger select, pre-trigger condition, and filter options. This Single-shot capture replaces the basic capture in prior FPGA versions. Some FPGAs support an additional Auto-arm mode. When enabled by software, Auto-arm uses a capture buffer memory to store multiple capture events (replaces the Probe module in prior FPGA versions).

The new trigger logic is common to all FPGAs (and slightly different to prior FPGA versions). Up to 32 trigger source inputs are available. The exact set of trigger source signals depends on the IO for each node. A trigger event can be selected from any input, with rising, falling, or both edges active. An optional filter function can be used to deglitch the signal. An optional pre-condition (based on the same trigger sources) can be specified: pre-condition high, low, rising edge, falling edge, or both.

For more information about using the new capture features, see Capture Objects.

Description:
Adds support for Mitutoyo serial digital interface rotary, linear, and absolute encoders.

Problem/Cause:
The drivePll may fail to lock for some unusual drive:controller ratios such as 22:1 (for example, 24 kHz drive with 1090 Hz controller). Drive communication will not be enabled. It is not possible to enable the drive. Motor status typically indicates Amp_Fault.

For certain controller rates, the MPI roundoff results in errors outside the drivePll phase detection range and the drivePll fails to lock.

Fix/Solution:

The drivePll module in the FPGA source code was upgraded with a phase detect range of +/-31 counts, which will support any drive:controller ratio from 1:1 to 32:1 (drive rates up to 32 kHz and controller rates down to 1 kHz).

Description:
EnDat interface now supports EnDat 2.2 rotary and linear including absolute devices operating in EnDat 2.1 compatibility mode. The S200 SynqNet supports Aux feedback if the EnDat 2.2 encoder has 1 Vp-p analog outputs. Example devices are Heidenhain LC183 and LC182 EnDat 2.2 absolute linear encoders.

Description:

Custom feedback type was added.

Note: This feature is reserved for future use.

Description:
Improved recovery from overload or loss of synchronization for 1 Vp-p Sin-Cos feedback on J14.

Description:

Unused logic was removed from the FPGA to make space for other features. The compare module was never supported by software and is therefore removed. Since only one GPIO pin is an S200 output (GPIO bit 2, OOUT1), all other output muxes were removed.

Description:
The drivePll module was improved to lock for a wider range of driveUpdatePeriod:controllerPeriod ratios and greater initial period error. This upgrade allows up to a 32:1 ratio and initial error of up to 16 clocks (0.640 us). This upgrade will reliably lock for any drive update period or controller period supported in any software release to date. Prior to this upgrade, the drive interface for some nodes failed to lock for some controller sample rates.

For example, a drive with 16 kHz period (such as S200) would not reliably lock to the controller rate of 1066 Hz. This configuration has a 15:1 driveUpdatePeriod:controllerPeriod ratio, and for various software reasons has a larger-than-normal initial period error. Problem ratios (and controller periods assuming a 16 kHz drive update period) are: 15:1 (1066 Hz), 14:1 (1142 Hz), 13:1 (1230 Hz). Marginal ratios are: 12:1 (1333 Hz), 11:1 (1454 Hz), 9:1 (1777 Hz), and 7:1 (2285 Hz). The marginal ratios may fail depending on the accuracy of the controller and node oscillators. When drivePll acquistion fails, the drive will not get the cyclic flag Drive_Strobe_Lock=1, and will not return the cyclic status Drive_Ready=1. The motor status indicates Amp_Fault and the motor cannot be enabled.

Problem/Cause:
The S200 EnDat encoder logic may have position offset errors at initialization under some conditions. The result may appear as a position "jump" to the user or application. This only occurs when:

1. EnDat 2.1 encoder feedback is used
2. Feedback is changing
3. SynqNet initialization (or controller reset) occurs
   

Problem/Cause:
When reading the monitor pointer values, the data was not returned through the whole service command handshake. In the FPGA, the data is written into a double buffered dual port memory. Depending upon which buffer the data ends up in, and which buffer the controller reads from, it determines whether or not the pointer value is correctly returned. Whether or not the controller reads the buffer that contained the correct data is dependent upon the network configuration, sample rate and the controller TX time.

Fix/Solution:
The source code was corrected for future FPGA versions.

Fix/Solution:
All data from service command reads are now latched in the driveInterfaceParallelMaster module so that they can be written to the double buffered drive memory module every drivePll period.

Fix/Solution:
Changes have been made so that the Brake Output bit is now enabled whenever the S200 amplifier is disabled. ReadyForRemoteControl (inverse of NotAmpPowered) is now active when either the driveFault or DINP1 is active. There was also a related MPI software change to modify the default state of the fault mask bit for Amp Not Powered. See MPI 1936 for more information.
This bit can also be set from Motion Console (or application) for older MPIs which leave it off by default.

Fix/Solution:
The FPGA logic has been corrected in FPGA version 0x0400_02_01 and later.

Fix/Solution:
In FPGA version 0x0400_02_00 and later, the FPGA module was changed to issue only one read or write command to the base unit per service channel access.

Description:
On the S200 SynqNet Option card, the home, posLimit, and negLimit inputs use opto isolator inputs with slow rise times to drive FPGA logic. The opto circuits were slow enough to cause glitching in the FPGA while the input value passed through the FPGA input threshold region. This glitching could cause false triggers in the capture engine. To compensate for the slow rise time of the opto isolator inputs, glitch filters were added on home, pos_lim, and neg_lim. The filter blocks pulses less that 35 µs in width (inputs are delayed a minimum of 35 µs, maximum of 41 µs).

For more information, see S200: Open Issues.

Fix/Solution:
The FPGA bit, driveResetComplete, has been removed from the dedicatedIo Fault and Fault Mask registers. This bit has been replaced with driveBootComplete in the dedicatedIo Config register. This bit is monitored solely by the sqNodeLib utility. It is currently not visible through MPI calls or through Motion Console.
NOTE: This change causes compatibility issues between new FPGAs and old software (or old FPGAs with new software). FPGA version x0400 and later require the 03.04.00 MPI software release and later.

Fix/Solution:
The FPGA was changed so that if the watchdog fault was the trigger to enter into the stop mode, the watchdog fault would not disable itself, thus allowing the fault to stay latched and also trigger the nodeIo fault.

Description:
The sqNode x0400 FPGA release introduces an upgraded network module, sqMac version 0300. Upgraded features include:

• SynqNet HotReplace - allows one or more more nodes to be shutdown, replaced, and brought back on-line without interrupting other nodes.
• Revised Cable Length Discovery - a new node-to-node method was added to make discovery more accurate.
• sqPll shutdown - a controlled shutdown of individual nodes for HotReplace.

The sqMac 0300 version is NOT fully compatible with MPI versions prior to 03.04.00. Using 0300 sqMac with older software (for some configurations) might cause the "idle cable" check function to accidently corrupt normal packet traffic. But, the MPI will issue a warning if old/new FPGA/MPI are mixed by accident.

Fix/Solution:
In FPGA version 0x0400 and later, the data returned as the 32-bit SFD feedback word is changed to the lower 8 bits of multi-turn data and all 24 bits of revolution data. This FPGA is being released with the 64-bit position feature of 03.04.00 MPI software release.

NOTE: By changing the resolution of the feedback word, tuning parameters will also need to change.

Fix/Solution:
In FPGA versions 0x0400 and later, the notAmpPowered fault bit is now latched. If active, it can be cleared by writing a "1" to bit 5 of the dedicatedIo fault status register.

NOTE: FPGA version 0x0400 and later require MPI software release 03.04.00 or later.

Description:
In FPGAs 0x0347, 0x0400, and later, the maximum quadrature encoder count rate has been improved to be 50MHz. In previous FPGA releases, the maximum count rate was 25MHz.

Fix/Solution:
The FPGA code was corrected to use the Valid bit. This fix exists in FPGA versions 0x0346_00_02 and later. No software changes are required.

Fix/Solution:
The driveFault bit from the drive may take from 52.4ms to 104.9ms to clear. The FPGA was changed to hold off the DONE bit on this command for 105ms to allow for this variance.

Fix/Solution:
In FPGA version x0346 and later, an ioAbort event still forces gpio "output" pins to "input" mode, which allows external resistors to pull pins from either high or low for a "safe" state. The resistors may or may not be present depending on the PCB assembly. However, during an ioAbort event, service writes to the gpio configuration register no longer cause momentary "output" direction. After the ioAbort event is cleared, gpio pins will resume their previous "output" state without software intervention.

Fix/Solution:
The FPGA code was corrected in version x0346 and later releases. This fix is required for systems using the Dual String or IN Port String topologies. This fix is NOT required for systems using normal OUT Port String or Ring topologies.

Description:
0x00 will be read for dataType NULL in the status and feedback packets.

Fix/Solution:
The fault recovery problems was corrected in FPGA build versions x0346 and later. The rcvMiiBuffer will correctly clear itself after an overflow. The xmitMiiReg will release xmitHoldRcvBuf within 8 clocks after a fault, preventing an rcvMiiBuffer overflow. 8 clocks will guarantee that there is minimum packet spacing between the packets. sqPll will ignore the second SYNQ packet after fault recovery (in case packet delays were effected in the cycle where fault recovery occurred). The rcvMii will correctly handle a valid packet with data length of 0. No software changes are required.

Description:
Changed the pin location for gpio0_z[2] from T10 to G13. Changed the pin location for gpio0_z[13] from K5 to T10. Changed number of gpioBits from 13 to 14. This change applies to FPGA version x0346 and later.

Problem/Cause:
If nodeAlarm is configured to look at the axis fault, and the axis fault is configured to look at driveFault, a race condition would occur making both nodeAlarm and driveFault unclearable. This issue existed in all FPGA versions prior to x0344.

Fix/Solution:
Modified FPGA code for versions x0344 and later. If a driveFault is occurring, nodeAlarm is not written to the drive. This allows for both nodeAlarm and driveFault to be cleared. No software changes are required.

Description:
Add support for multiple packets to the rxMiiBuffer. This improves tolerance to network jitter. Prior to version x0341, the rxMiiBuffer could absorb up to 32 clocks (1.28 µS) of delay for a single packet, but only 8 clocks for multiple packets with minimum spacing. This change is required to meet theoretical worst-case network jitter in large networks (32 nodes). The improvement may also help at network startup, since the node's PLL phase error is larger than normal (as the PLL pulls into nominal lock). No software changes are required.

Description:
Release new FPGA type C0FE0036_0341.sff.

Description:
Add BranchRev register. This extends the existing 16 bits of FPGA version number with 8 bits of branch and 8 bits of revision ID.