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Release Note
C0FE0035_xxxx.sff

MPI Version
FPGA Version
04.00.00
Production Release
C0FE0035_0500
03.04.00
Production Release
C0FE0035_0400
03.03.00
Production Release
C0FE0035_0346
03.02.00
Production Release
C0FE0035_0343

  Table of Contents
     
    Changes and Bug Fixes
     

C0FE0035_0500
     sqMac upgraded to support 64 nodes - New Feature - FP886
     Improved Capture module unified with Probe features - General Change - FP823

C0FE0035_0400
     Remove drive reset complete from the fault and fault mask registers - General Change - FP466 
     The watchdog fault was incorrectly being cleared after being activated - Bug Fix- FP465
     sqMac Version 0300 - New Feature - FP407
     Latch added on the notAmpPowered bit - General Change - FP402
     Connect driveStatusFlag9, driveStatus10 between driveMemory and dedicatedIo - Bug Fix - FP394
     Support for a maximum count rate of 50MHz without filters - New Feature - FP337

C0FE0035_0346
     Modifications to gpioPinConfigReg - General Change - FP336
     Intermittent Dual String Discovery failure - Bug Fix - FP332
     sqMac - 0x00 will be read for dataType NULL - New Feature - FP323
     Intermittent Fault Recovery failures - Bug Fix - FP315
     Support for captureFast (probe) - New Feature - FP312

C0FE0035_0343
     C0FE0035 GPIO increased to 16, primary quadrature removed - Bug Fix - FP278

C0FE0035_0341
     sqMac rxMiiBuffer multiple packets - General Change - FP263

C0FE0035_0340
     New BranchRev Register - New Feature - FP231
     New FPGA C0FE0035 - New Feature - FP214


C0FE0035_0500

  sqMac upgraded to support 64 nodes
    Reference Number: FP 886
    Type: New Feature
    FPGA Version: 0x0500
   

Description

The sqMac module (the network interface logic) was upgraded to support up to 64 nodes. Key changes include:

larger packet forwarding buffer. Previously 128 bits deep, now 2048 bits (Spartan2/2e) or 8196 bits (Spartan3/3e).

Improved support for pipelined service commands.


  Improved Capture module unified with Probe features
    Reference Number: FP 823
    Type: General Change
    FPGA Version: 0x0500
    Description:

A new unified Capture module was created to replace the older versions of both the Capture and Probe modules. In addition, new trigger features were introduced.

All Capture modules have a base feature set: Single-shot capture with the new trigger select, pre-trigger condition, and filter options. This Single-shot capture replaces the basic capture in prior FPGA versions. Some FPGAs support an additional Auto-arm mode. When enabled by software, Auto-arm uses a capture buffer memory to store multiple capture events (replaces the Probe module in prior FPGA versions).

The new trigger logic is common to all FPGAs (and slightly different to prior FPGA versions). Up to 32 trigger source inputs are available. The exact set of trigger source signals depends on the IO for each node. A trigger event can be selected from any input, with rising, falling, or both edges active. An optional filter function can be used to deglitch the signal. An optional pre-condition (based on the same trigger sources) can be specified: pre-condition high, low, rising edge, falling edge, or both.

For more information about using the new capture features, see Capture Objects.

 

C0FE0035_0400

  Remove drive reset complete from the fault and fault mask registers
    Reference Number: FP 466
    Type: General Change
    FPGA Version: 0x0400
    Problem/Cause:
As more drives require a driveBootComplete bit to indicate when they are finished booting, it was necessary to change the current bit to a more ideal location.
   

Fix/Solution:
The FPGA bit, driveResetComplete, has been removed from the dedicatedIo Fault and Fault Mask registers. This bit has been replaced with driveBootComplete in the dedicatedIo Config register. This bit is monitored solely by the sqNodeLib utility. It is currently not visible through MPI calls or through Motion Console.
NOTE: This change causes compatibility issues between new FPGAs and old software (or old FPGAs with new software). FPGA version x0400 and later require the 03.04.00 MPI software release and later.


  The watchdog fault was incorrectly being cleared after being activated
    Reference Number: FP 465
    Type: Bug Fix
    FPGA Version: 0x0400
    Problem/Cause:
The Slice I/O watchdog fault was incorrectly being cleared after being activated. If a watchdog fault occurred, the FPGA would send a stop command to all slices to halt cyclic operation. As a result of being in this stop mode, it would cause the watchdog fault to be disabled and incorrectly clear itself. Therefore, the fault would never be seen.
   

Fix/Solution:
The FPGA was changed so that if the watchdog fault was the trigger to enter into the stop mode, the watchdog fault would not disable itself, thus allowing the fault to stay latched and also trigger the nodeIo fault.


  sqMac Version 0300
    Reference Number: FP 407
    Type: New Feature
    FPGA Version: 0x0400
   

Description:
The sqNode x0400 FPGA release introduces an upgraded network module, sqMac version 0300. Upgraded features include:

  • SynqNet HotReplace - allows one or more more nodes to be shutdown, replaced, and brought back on-line without interrupting other nodes.
  • Revised Cable Length Discovery - a new node-to-node method was added to make discovery more accurate.
  • sqPll shutdown - a controlled shutdown of individual nodes for HotReplace.

The sqMac 0300 version is NOT fully compatible with MPI versions prior to 03.04.00. Using 0300 sqMac with older software (for some configurations) might cause the "idle cable" check function to accidently corrupt normal packet traffic. But, the MPI will issue a warning if old/new FPGA/MPI are mixed by accident.


  Latch added on the notAmpPowered bit
    Reference Number: FP 402
    Type: General Change
    FPGA Version: 0x0400
    Problem/Cause:
In FPGA versions previous to 0x0400, the notAmpPowered fault bit was not latched.
   

Fix/Solution:
In FPGA versions 0x0400 and later, the notAmpPowered fault bit is now latched. If active, it can be cleared by writing a "1" to bit 5 of the dedicatedIo fault status register.


  Connect driveStatusFlag9, driveStatus10 between driveMemory and dedicatedIo
    Reference Number: FP 394
    Type: Bug Fix
    FPGA Version: 0x0346_00_03; 0x0400
    Problem/Cause:
Prior to FPGA version 0x0346_00_03, and 0x0400 the driveStatusFlag9 and driveStatusFlag10 bits were always forced to "0." These status bits were used for "Autonomous_Drive_Action_Complete" and "Reserved for drive specfic features."
   

Fix/Solution:
In FPGA version 0x0346_00_03, 0x0400 and later, the driveStatusFlag9 and driveStatusFlag10 bits are controlled by the drive processor.


  Support for a maximum count rate of 50MHz without filters
    Reference Number: FP 337
    Type: New Feature
    FPGA Version: 0x0347; 0x0400
   

Description:
In FPGAs 0x0347, 0x0400, and later, the maximum quadrature encoder count rate has been improved to be 50MHz. In previous FPGA releases, the maximum count rate was 25MHz.

 

C0FE0035_0346

  Modications to gpioPinConfigReg
    Reference Number: FP 336
    Type: General Change
    FPGA Version: 0x0346
    Problem/Cause:
Prior to FPGA version x0346, gpio pins that were configured as an "output" did not resume "output" direction after an ioAbort event. Also, during the ioAbort event, if a service channel write to the gpio configuration register occurred, the gpio "output" pins would be set to "output" mode momentarily (and then cleared to "input" mode by the ioAbort event). After the ioAbort event was cleared, the gpio pin state would remain as in "input" mode unless software restored the gpio configuration register again.
   

Fix/Solution:
In FPGA version x0346 and later, an ioAbort event still forces gpio "output" pins to "input" mode, which allows external resistors to pull pins from either high or low for a "safe" state. The resistors may or may not be present depending on the PCB assembly. However, during an ioAbort event, service writes to the gpio configuration register no longer cause momentary "output" direction. After the ioAbort event is cleared, gpio pins will resume their previous "output" state without software intervention.


  Intermittent Dual String Discovery Failure
    Reference Number: FP 332
    Type: Bug Fix
    FPGA Version: 0x0346
    Problem/Cause:
Probe, resetRequest, and resetComplete were repeated on the wrong port (OUT port) when using the OUT port as the primary port during SynqNet node discovery. As a result, SynqNet node discovery may have failed. This problem was caused by the probe, resetRequest, and resetComplete being repeated on the wrong port. This issue existed in all FPGA versions prior to x0346.
   

Fix/Solution:
The FPGA code was corrected in version x0346 and later releases. This fix is required for systems using the Dual String or IN Port String topologies. This fix is NOT required for systems using normal OUT Port String or Ring topologies.


  sqMac - 0x00 will be read for dataType NULL
    Reference Number: FP 323
    Type: New Feature
    FPGA Version: 0x0346
   

Description:
0x00 will be read for dataType NULL in the status and feedback packets.


  Intermittent Fault Recovery failures
    Reference Number: FP 315
    Type: Bug Fix
    FPGA Version: 0x0346
    Problem/Cause:
Some nodes may have intermittently failed to recover from a fault in some network configurations. If a node failed to recover, it exited cyclic operation and correctly triggered ioAbort logic (forcing outputs into "safe" states). Any nodes "downstream" of the failing node (after it switched ports) were also likely to exit cyclic operation. For any given node, there was only a small schedule window where this error may have occurred. There were two causes of the problem. The rcvMiiBuffer did not clear itself after an overflow in some situations. Also, a packet fragment generated by the fault recovery that happened to have valid CRC (but no data) would confuse the packetFifo, and corrupt internal node configuration bits. The first issue existed in FPGA build versions x0341 through x0345 and their branches (MPI release 03.02.00). The second issue existed in all FPGA versions prior to x0346.
   

Fix/Solution:
The fault recovery problems was corrected in FPGA build versions x0346 and later. The rcvMiiBuffer will correctly clear itself after an overflow. The xmitMiiReg will release xmitHoldRcvBuf within 8 clocks after a fault, preventing an rcvMiiBuffer overflow. 8 clocks will guarantee that there is minimum packet spacing between the packets. sqPll will ignore the second SYNQ packet after fault recovery (in case packet delays were effected in the cycle where fault recovery occurred). The rcvMii will correctly handle a valid packet with data length of 0. No software changes are required.


  Support for captureFast (probe)
    Reference Number: FP 312
    Type: New Feature
    FPGA Version: 0x0346
   

Description:
Addition of captureFast (probe) support.

 

C0FE0035_0343

  C0FE0035 GPIO increased to 16, primary quadrature removed
    Reference Number: FP 278
    Type: Bug Fix
    FPGA Version: 0x0343
   

Problem/Cause:
C0FE0035 pins gpio0_z[8:15] and gpio1_z[8:15] are not functional (only 8 GPIO pins per motor were instantiated). Also, primary quadrature feedback is instantiated for both motors (specification calls for no primary quadrature logic). These problems existed in all versions of C0FE0035 prior to x0343.

   

Fix/Solution:
FPGA code was corrected to instantiate 16 GPIO pins per motor, and remove primary feedback quadrature logic. This fix is included in versions x0343 and later. No software changes are required.

 

C0FE0035_0341

  sqMac rxMiiBuffer multiple packets
    Reference Number: FP 263
    Type: General Change
    FPGA Version: 0x0341
   

Description:
Add support for multiple packets to the rxMiiBuffer. This improves tolerance to network jitter. Prior to version x0341, the rxMiiBuffer could absorb up to 32 clocks (1.28 µS) of delay for a single packet, but only 8 clocks for multiple packets with minimum spacing. This change is required to meet theoretical worst-case network jitter in large networks (32 nodes). The improvement may also help at network startup, since the node's PLL phase error is larger than normal (as the PLL pulls into nominal lock). No software changes are required.

 

C0FE0035_0340

  New BranchRev Register
    Reference Number: FP 231
    Type: New Feature
    FPGA Version: 0x0340
   

Description:
Add BranchRev register. This extends the existing 16 bits of FPGA version number with 8 bits of branch and 8 bits of revision ID.


  New FPGA C0FE0035
    Reference Number: FP 214
    Type: New Feature
    FPGA Version: 0x0340
   

Description:
Release new FPGA type C0FE0035_0340.sff.

 

 

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