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Release Note
C0FE0030_xxxx.sff

MPI Version
FPGA Version
04.00.00
Production Release
C0FE0030_0500
03.04.00
Production Release
C0FE0030_0400
03.03.00
Production Release
C0FE0030_0346
03.02.00
Production Release
C0FE0030_0342

  Table of Contents
     
    Changes and Bug Fixes
     

C0FE0030_0500
     sqMac upgraded to support 64 nodes - New Feature - FP886

C0FE0030_0400
     Remove drive reset complete from the fault and fault mask registers - General Change - FP466 
     The watchdog fault was incorrectly being cleared after being activated - Bug Fix- FP465
     Logic added to detect and report faults - New Feature - FP414
     sqMac Version 0300 - New Feature - FP407

C0FE0030_0346
     Intermittent Dual String Discovery failure - Bug Fix - FP332
     sqMac - 0x00 will be read for dataType NULL - New Feature - FP323
     Intermittent Fault Recovery failures - Bug Fix - FP315
     nodeIoSpi - State machine hangs during an SPI cycle - Bug Fix - FP290

C0FE0030_0342
     nodeIoSpi transmit buffer clock - Bug Fix - FP269

C0FE0030_0341
     sqMac rxMiiBuffer multiple packets - General Change - FP263
     nodeIoSpi 12.5MHz SPI bus - General Change - FP245

C0FE0030_0340
     New BranchRev Register - New Feature - FP231

 

C0FE0030_0500

  sqMac upgraded to support 64 nodes
    Reference Number: FP 886
    Type: New Feature
    FPGA Version: 0x0500
   

Description

The sqMac module (the network interface logic) was upgraded to support up to 64 nodes. Key changes include:

larger packet forwarding buffer. Previously 128 bits deep, now 2048 bits (Spartan2/2e) or 8196 bits (Spartan3/3e).

Improved support for pipelined service commands.

 

C0FE0030_0400

  Remove drive reset complete from the fault and fault mask registers
    Reference Number: FP 466
    Type: General Change
    FPGA Version: 0x0400
    Problem/Cause:
As more drives require a driveBootComplete bit to indicate when they are finished booting, it was necessary to change the current bit to a more ideal location.
   

Fix/Solution:
The FPGA bit, driveResetComplete, has been removed from the dedicatedIo Fault and Fault Mask registers. This bit has been replaced with driveBootComplete in the dedicatedIo Config register. This bit is monitored solely by the sqNodeLib utility. It is currently not visible through MPI calls or through Motion Console.
NOTE: This change causes compatibility issues between new FPGAs and old software (or old FPGAs with new software). FPGA version x0400 and later require the 03.04.00 MPI software release and later.


  The watchdog fault was incorrectly being cleared after being activated
    Reference Number: FP 465
    Type: Bug Fix
    FPGA Version: 0x0400
    Problem/Cause:
The Slice I/O watchdog fault was incorrectly being cleared after being activated. If a watchdog fault occurred, the FPGA would send a stop command to all slices to halt cyclic operation. As a result of being in this stop mode, it would cause the watchdog fault to be disabled and incorrectly clear itself. Therefore, the fault would never be seen.
   

Fix/Solution:
The FPGA was changed so that if the watchdog fault was the trigger to enter into the stop mode, the watchdog fault would not disable itself, thus allowing the fault to stay latched and also trigger the nodeIo fault.


  Logic added to detect and report faults
    Reference Number: FP 414
    Type: New Feature
    FPGA Version: 0x0400
   

Description:
Added support for the following SQID I/O faults:

  1. Input Clock Timeout
    In FPGA versions prior to x0400, the logic could enter an infinite wait cycle if the input clock disappeared in the middle of a transaction. To solve this problem, a timeout was added to determine if the input clock stopped. A nodeIoFault will now occur and cause the input and output state machines to enter a fault mode, thus avoiding the infinite wait cycle. This fault will also cause the output enable bit to be inactive, thus causing all outputs to go to a known state. The fault bit also has a software disable for debug environments.
  2. To make the serial stream more robust, logic was added to check the start/stop bits cyclically. In previous versions, they were only checked at discovery time.

  sqMac Version 0300
    Reference Number: FP 407
    Type: New Feature
    FPGA Version: 0x0400
   

Description:
The sqNode x0400 FPGA release introduces an upgraded network module, sqMac version 0300. Upgraded features include:

  • SynqNet HotReplace - allows one or more more nodes to be shutdown, replaced, and brought back on-line without interrupting other nodes.
  • Revised Cable Length Discovery - a new node-to-node method was added to make discovery more accurate.
  • sqPll shutdown - a controlled shutdown of individual nodes for HotReplace.

The sqMac 0300 version is NOT fully compatible with MPI versions prior to 03.04.00. Using 0300 sqMac with older software (for some configurations) might cause the "idle cable" check function to accidently corrupt normal packet traffic. But, the MPI will issue a warning if old/new FPGA/MPI are mixed by accident.

 

C0FE0030_0346

  Intermittent Dual String Discovery Failure
    Reference Number: FP 332
    Type: Bug Fix
    FPGA Version: 0x0346
    Problem/Cause:
Probe, resetRequest, and resetComplete were repeated on the wrong port (OUT port) when using the OUT port as the primary port during SynqNet node discovery. As a result, SynqNet node discovery may have failed. This problem was caused by the probe, resetRequest, and resetComplete being repeated on the wrong port. This issue existed in all FPGA versions prior to x0346.
   

Fix/Solution:
The FPGA code was corrected in version x0346 and later releases. This fix is required for systems using the Dual String or IN Port String topologies. This fix is NOT required for systems using normal OUT Port String or Ring topologies.


  sqMac - 0x00 will be read for dataType NULL
    Reference Number: FP 323
    Type: New Feature
    FPGA Version: 0x0346
   

Description:
0x00 will be read for dataType NULL in the status and feedback packets.


  Intermittent Fault Recovery failures
    Reference Number: FP 315
    Type: Bug Fix
    FPGA Version: 0x0346
    Problem/Cause:
Some nodes may have intermittently failed to recover from a fault in some network configurations. If a node failed to recover, it exited cyclic operation and correctly triggered ioAbort logic (forcing outputs into "safe" states). Any nodes "downstream" of the failing node (after it switched ports) were also likely to exit cyclic operation. For any given node, there was only a small schedule window where this error may have occurred. There were two causes of the problem. The rcvMiiBuffer did not clear itself after an overflow in some situations. Also, a packet fragment generated by the fault recovery that happened to have valid CRC (but no data) would confuse the packetFifo, and corrupt internal node configuration bits. The first issue existed in FPGA build versions x0341 through x0345 and their branches (MPI release 03.02.00). The second issue existed in all FPGA versions prior to x0346.
   

Fix/Solution:
The fault recovery problems have been fixed in FPGA build versions x0346 and later. The rcvMiiBuffer will correctly clear itself after an overflow. The xmitMiiReg will release xmitHoldRcvBuf within 8 clocks after a fault, preventing an rcvMiiBuffer overflow. 8 clocks will guarantee that there is minimum packet spacing between the packets. sqPll will ignore the second SYNQ packet after fault recovery (in case packet delays were effected in the cycle where fault recovery occurred). The rcvMii will correctly handle a valid packet with data length of 0. No software changes are required.


  nodeIoSpi - State machine hangs during an SPI cycle
    Reference Number: FP 290
    Type: Bug Fix
    FPGA Version: 0x0346
    Problem/Cause:
NodeIo digital inputs or analog inputs may have stopped updating in certain situations. If the start bits were enabled during a SPI cycle, the receive state machine would hang. This problem occurred because at the beginning of the cycle, the start bits were not enabled. Therefore, the transmit engine did not send the start bits. By the end of the cycle, the start bits were enabled, causing the receive engine to wait for the bits to arrive. As a result, the receive engine was stuck in this wait state. This issue existed prior to FPGA release x0346.
   

Fix/Solution:
The FPGA design has been fixed in FPGA release x0346 and later.


 

C0FE0030_0342

  nodeIoSpi transmit buffer clock
    Reference Number: FP 269
    Type: Bug Fix
    FPGA Version: 0x0342
   

Problem/Cause:
C0FE0030 SPI bus transmit data may be corrupted. The dual port buffer logic was running on 25 MHz clock instead of 50 MHz clock. This problem only exists in version x0341.

   

Problem/Cause:
FPGA code was corrected to use 50 MHz clock. This fix is in version x0342 and later. No software changes are required.

 

C0FE0030_0341

  sqMac rxMiiBuffer multiple packets
    Reference Number: FP 263
    Type: General Change
    FPGA Version: 0x0341
   

Description:
Add support for multiple packets to the rxMiiBuffer. This improves tolerance to network jitter. Prior to version x0341, the rxMiiBuffer could absorb up to 32 clocks (1.28 µS) of delay for a single packet, but only 8 clocks for multiple packets with minimum spacing. This change is required to meet theoretical worst-case network jitter in large networks (32 nodes). The improvement may also help at network startup, since the node's PLL phase error is larger than normal (as the PLL pulls into nominal lock). No software changes are required.


  nodeIoSpi 12.5MHz SPI bus
    Reference Number: FP 245
    Type: General Change
    FPGA Version: 0x0341
   

Problem/Cause:
The nodeIoSpi module does not work correctly when configured for a 12.5 MHz SPI bus clock rate.

   

Fix/Solution:
The FPGA code was modifed to use a 50 MHz clock rate in the nodeIoSpi module, allowing 12.5 MHz SPI bus clock rate in FPGA versions x0341 and later. No software changes are required.

 

C0FE0030_0340

  New BranchRev Register
    Reference Number: FP 231
    Type: New Feature
    FPGA Version: 0x0340
   

Description:
Add BranchRev register. This extends the existing 16 bits of FPGA version number with 8 bits of branch and 8 bits of revision ID.

 

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