Problem/Cause:

The driveClkInvert cannot be read back by service command. Writes work correctly, however the read value is always 0.

This bit was added to the driveInterfaceSerial module in sqNode Build 0400_03_02. However, the read path was missing from the FPGA source code.

Fix/Solution:
The FPGA logic was corrected.

Description:

This feature is only relavant to drives that require clock inversion to set the correct boot source. For example drives that use TMS320F2801 as listed below.

The drive serial interface has a clock output which is low when clocks are not being emitted.
Unfortunately on the TMS320F2801 processor, the SPI clock input pin is also a boot control pin and for the DSP to boot normally this pin must be high. To permit this a further bit was added to the clkCfg register (bit 5) which inverts the driveClk output.

Kollmorgen MSM4 C0FE0043
Kollmorgen NIM-MSM1-V2 C0FE0045
Kollmorgen NIM-MSM1-V3 C0FE0045
Kollmorgen NIM-V2 C0FE0045
Kollmorgen NIM-V3 C0FE0045
Kollmorgen NIM-LAM2-V2 C0FE0045
Kollmorgen NIM-LAM2-V3 C0FE0045