Problem/Cause:

The driveClkInvert cannot be read back by service command. Writes work correctly, however the read value is always 0.

This bit was added to the driveInterfaceSerial module in sqNode Build 0400_03_02. However, the read path was missing from the FPGA source code.

Fix/Solution:
The FPGA logic was corrected.

Description:

This feature is only relavant to drives that require clock inversion to set the correct boot source. For example drives that use TMS320F2801 as listed below.

The drive serial interface has a clock output which is low when clocks are not being emitted.
Unfortunately on the TMS320F2801 processor, the SPI clock input pin is also a boot control pin and for the DSP to boot normally this pin must be high. To permit this a further bit was added to the clkCfg register (bit 5) which inverts the driveClk output.

Kollmorgen MSM4 C0FE0043
Kollmorgen NIM-MSM1-V2 C0FE0045
Kollmorgen NIM-MSM1-V3 C0FE0045
Kollmorgen NIM-V2 C0FE0045
Kollmorgen NIM-V3 C0FE0045
Kollmorgen NIM-LAM2-V2 C0FE0045
Kollmorgen NIM-LAM2-V3 C0FE0045

Problem/Cause:

The checksum error status for drives 1, 2, and 3 was not mapped to axis 1, 2, 3.

In FPGA version 0400_03_00, checksum error from drives 0 and 1 was mapped to the dedicated I/O for Axis 0. Checksum error for drives 2 and 3 were mapped to dedicated I/O for Axis 1. No error was mapped to dedicated I/O Axis 2 or 3.

Fix/Solution:
The FPGA source code was corrected.

Problem/Cause:

The drive interface flag bit Demand_Strobe_Flag is incorrectly asserted even when a DEMAND packet is missing.

The SynqNet Drive Interface specification defines the Demand_Strobe_Flag as asserted for each new demand value from the controller. For example, a 4 kHz controller cycle with a 16 kHz drive would assert Demand_Strobe_Flag on every 4th Drive_Strobe. In addition, a missing DEMAND packet causes a repeated demand value resulting in a missing Demand_Strobe_Flag since no new value is presented. This allows drives to correctly track the rate of change in demands. This fault existed in all prior versions of all FPGAs.

Fix/Solution:
The FPGA source code has been corrected.

Description:

The drivePll module was improved to lock for a wider range of driveUpdatePeriod:controllerPeriod ratios and greater initial period error. This upgrade allows up to a 32:1 ratio and initial error of up to 16 clocks (0.640 us). This upgrade will reliably lock for any drive update period or controller period supported in any software release to date. Prior to this upgrade, the drive interface for some nodes failed to lock for some controller sample rates.

For example, a drive with 16 kHz period (such as S200) would not reliably lock to the controller rate of 1066 Hz. This configuration has a 15:1 driveUpdatePeriod:controllerPeriod ratio, and for various software reasons has a larger-than-normal initial period error. Problem ratios (and controller periods assuming a 16 kHz drive update period) are: 15:1 (1066 Hz), 14:1 (1142 Hz), 13:1 (1230 Hz). Marginal ratios are: 12:1 (1333 Hz), 11:1 (1454 Hz), 9:1 (1777 Hz), and 7:1 (2285 Hz). The marginal ratios may fail depending on the accuracy of the controller and node oscillators. When drivePll acquistion fails, the drive will not get the cyclic flag Drive_Strobe_Lock=1, and will not return the cyclic status Drive_Ready=1. The motor status indicates Amp_Fault and the motor cannot be enabled.