Fix/Solution:
The FPGA bit, driveResetComplete, has been removed from the dedicatedIo Fault and Fault Mask registers. This bit has been replaced with driveBootComplete in the dedicatedIo Config register. This bit is monitored solely by the sqNodeLib utility. It is currently not visible through MPI calls or through Motion Console.
NOTE: This change causes compatibility issues between new FPGAs and old software (or old FPGAs with new software). FPGA version x0400 and later require the 03.04.00 MPI software release and later.

Fix/Solution:
The FPGA was changed so that if the watchdog fault was the trigger to enter into the stop mode, the watchdog fault would not disable itself, thus allowing the fault to stay latched and also trigger the nodeIo fault.

Description:
The sqNode x0400 FPGA release introduces an upgraded network module, sqMac version 0300. Upgraded features include:

• SynqNet HotReplace - allows one or more more nodes to be shutdown, replaced, and brought back on-line without interrupting other nodes.
• Revised Cable Length Discovery - a new node-to-node method was added to make discovery more accurate.
• sqPll shutdown - a controlled shutdown of individual nodes for HotReplace.

The sqMac 0300 version is NOT fully compatible with MPI versions prior to 03.04.00. Using 0300 sqMac with older software (for some configurations) might cause the "idle cable" check function to accidently corrupt normal packet traffic. But, the MPI will issue a warning if old/new FPGA/MPI are mixed by accident.

Fix/Solution:
In FPGA versions 0x0400 and later, the notAmpPowered fault bit is now latched. If active, it can be cleared by writing a "1" to bit 5 of the dedicatedIo fault status register.

Description:
In FPGAs 0x0347, 0x0400, and later, the maximum quadrature encoder count rate has been improved to be 50MHz. In previous FPGA releases, the maximum count rate was 25MHz.

Fix/Solution:
In FPGA version x0346 and later, an ioAbort event still forces gpio "output" pins to "input" mode, which allows external resistors to pull pins from either high or low for a "safe" state. The resistors may or may not be present depending on the PCB assembly. However, during an ioAbort event, service writes to the gpio configuration register no longer cause momentary "output" direction. After the ioAbort event is cleared, gpio pins will resume their previous "output" state without software intervention.

Fix/Solution:
The FPGA code was corrected in version x0346 and later releases. This fix is required for systems using the Dual String or IN Port String topologies. This fix is NOT required for systems using normal OUT Port String or Ring topologies.

Description:
0x00 will be read for dataType NULL in the status and feedback packets.

Fix/Solution:
The fault recovery problems was corrected in FPGA build versions x0346 and later. The rcvMiiBuffer will correctly clear itself after an overflow. The xmitMiiReg will release xmitHoldRcvBuf within 8 clocks after a fault, preventing an rcvMiiBuffer overflow. 8 clocks will guarantee that there is minimum packet spacing between the packets. sqPll will ignore the second SYNQ packet after fault recovery (in case packet delays were effected in the cycle where fault recovery occurred). The rcvMii will correctly handle a valid packet with data length of 0. No software changes are required.

Description:
Support has been added for big endian or little endian byte ordering in the driveParallel interface.

Description:
Add support for multiple packets to the rxMiiBuffer. This improves tolerance to network jitter. Prior to version x0341, the rxMiiBuffer could absorb up to 32 clocks (1.28 µS) of delay for a single packet, but only 8 clocks for multiple packets with minimum spacing. This change is required to meet theoretical worst-case network jitter in large networks (32 nodes). The improvement may also help at network startup, since the node's PLL phase error is larger than normal (as the PLL pulls into nominal lock). No software changes are required.

Description:
Add BranchRev register. This extends the existing 16 bits of FPGA version number with 8 bits of branch and 8 bits of revision ID.