Fix/Solution:
The FPGA bit, driveResetComplete, has been removed from the dedicatedIo Fault and Fault Mask registers. This bit has been replaced with driveBootComplete in the dedicatedIo Config register. This bit is monitored solely by the sqNodeLib utility. It is currently not visible through MPI calls or through Motion Console.
NOTE: This change causes compatibility issues between new FPGAs and old software (or old FPGAs with new software). FPGA version x0400 and later require the 03.04.00 MPI software release and later.

Fix/Solution:
The FPGA was changed so that if the watchdog fault was the trigger to enter into the stop mode, the watchdog fault would not disable itself, thus allowing the fault to stay latched and also trigger the nodeIo fault.

Description:
Added support for the following SQID I/O faults:

1. Input Clock Timeout
   In FPGA versions prior to x0400, the logic could enter an infinite wait cycle if the input clock disappeared in the middle of a transaction. To solve this problem, a timeout was added to determine if the input clock stopped. A nodeIoFault will now occur and cause the input and output state machines to enter a fault mode, thus avoiding the infinite wait cycle. This fault will also cause the output enable bit to be inactive, thus causing all outputs to go to a known state. The fault bit also has a software disable for debug environments.
   
2. To make the serial stream more robust, logic was added to check the start/stop bits cyclically. In previous versions, they were only checked at discovery time.

Description:
The sqNode x0400 FPGA release introduces an upgraded network module, sqMac version 0300. Upgraded features include:

• SynqNet HotReplace - allows one or more more nodes to be shutdown, replaced, and brought back on-line without interrupting other nodes.
• Revised Cable Length Discovery - a new node-to-node method was added to make discovery more accurate.
• sqPll shutdown - a controlled shutdown of individual nodes for HotReplace.

The sqMac 0300 version is NOT fully compatible with MPI versions prior to 03.04.00. Using 0300 sqMac with older software (for some configurations) might cause the "idle cable" check function to accidently corrupt normal packet traffic. But, the MPI will issue a warning if old/new FPGA/MPI are mixed by accident.

Fix/Solution:
The FPGA code was corrected in version x0346 and later releases. This fix is required for systems using the Dual String or IN Port String topologies. This fix is NOT required for systems using normal OUT Port String or Ring topologies.

Description:
0x00 will be read for dataType NULL in the status and feedback packets.

Fix/Solution:
The fault recovery problems have been fixed in FPGA build versions x0346 and later. The rcvMiiBuffer will correctly clear itself after an overflow. The xmitMiiReg will release xmitHoldRcvBuf within 8 clocks after a fault, preventing an rcvMiiBuffer overflow. 8 clocks will guarantee that there is minimum packet spacing between the packets. sqPll will ignore the second SYNQ packet after fault recovery (in case packet delays were effected in the cycle where fault recovery occurred). The rcvMii will correctly handle a valid packet with data length of 0. No software changes are required.

Fix/Solution:
The FPGA design has been fixed in FPGA release x0346 and later.

Problem/Cause:
C0FE0030 SPI bus transmit data may be corrupted. The dual port buffer logic was running on 25 MHz clock instead of 50 MHz clock. This problem only exists in version x0341.

Problem/Cause:
FPGA code was corrected to use 50 MHz clock. This fix is in version x0342 and later. No software changes are required.

Description:
Add support for multiple packets to the rxMiiBuffer. This improves tolerance to network jitter. Prior to version x0341, the rxMiiBuffer could absorb up to 32 clocks (1.28 µS) of delay for a single packet, but only 8 clocks for multiple packets with minimum spacing. This change is required to meet theoretical worst-case network jitter in large networks (32 nodes). The improvement may also help at network startup, since the node's PLL phase error is larger than normal (as the PLL pulls into nominal lock). No software changes are required.

Problem/Cause:
The nodeIoSpi module does not work correctly when configured for a 12.5 MHz SPI bus clock rate.

Fix/Solution:
The FPGA code was modifed to use a 50 MHz clock rate in the nodeIoSpi module, allowing 12.5 MHz SPI bus clock rate in FPGA versions x0341 and later. No software changes are required.

Description:
Add BranchRev register. This extends the existing 16 bits of FPGA version number with 8 bits of branch and 8 bits of revision ID.