Release Note
C0FE0037_xxxx.sff
MPI Version |
FPGA Version |
03.03.00
Production Release |
C0FE0037_0346 |
C0FE0037_0346
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Modications to gpioPinConfigReg |
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Reference Number: FP 336 |
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Type: General Change |
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FPGA Version: 0x0346 |
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Problem/Cause:
Prior to FPGA version x0346, gpio pins that were configured as an "output" did not resume "output" direction after an ioAbort event. Also, during the ioAbort event, if a service channel write to the gpio configuration register occurred, the gpio "output" pins would be set to "output" mode momentarily (and then cleared to "input" mode by the ioAbort event). After the ioAbort event was cleared, the gpio pin state would remain as in "input" mode unless software restored the gpio configuration register again. |
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Fix/Solution:
In FPGA version x0346 and later, an ioAbort event still forces gpio "output" pins to "input" mode, which allows external resistors to pull pins from either high or low for a "safe" state. The resistors may or may not be present depending on the PCB assembly. However, during an ioAbort event, service writes to the gpio configuration register no longer cause momentary "output" direction. After the ioAbort event is cleared, gpio pins will resume their previous "output" state without software intervention.
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Intermittent Dual String Discovery Failure |
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Reference Number: FP 332 |
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Type: Bug Fix |
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FPGA Version: 0x0346 |
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Problem/Cause:
Probe, resetRequest, and resetComplete were repeated on the wrong port (OUT port) when using the OUT port as the primary port during SynqNet node discovery. As a result, SynqNet node discovery may have failed. This problem was caused by the probe, resetRequest, and resetComplete being repeated on the wrong port. This issue existed in all FPGA versions prior to x0346. |
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Fix/Solution:
The FPGA code was corrected in version x0346 and later releases. This fix is required for systems using the Dual String or IN Port String topologies. This fix is NOT required for systems using normal OUT Port String or Ring topologies.
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sqMac - 0x00 will be read for dataType NULL |
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Reference Number: FP 323 |
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Type: New Feature |
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FPGA Version: 0x0346 |
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Description:
0x00 will be read for dataType NULL in the status and feedback packets.
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Intermittent Fault Recovery failures |
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Reference Number: FP 315 |
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Type: Bug Fix |
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FPGA Version: 0x0346 |
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Problem/Cause:
Some nodes may have intermittently failed to recover from a fault in some network configurations. If a node failed to recover, it exited cyclic operation and correctly triggered ioAbort logic (forcing outputs into "safe" states). Any nodes "downstream" of the failing node (after it switched ports) were also likely to exit cyclic operation. For any given node, there was only a small schedule window where this error may have occurred. There were two causes of the problem. The rcvMiiBuffer did not clear itself after an overflow in some situations. Also, a packet fragment generated by the fault recovery that happened to have valid CRC (but no data) would confuse the packetFifo, and corrupt internal node configuration bits. The first issue existed in FPGA build versions x0341 through x0345 and their branches (MPI release 03.02.00). The second issue existed in all FPGA versions prior to x0346. |
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Fix/Solution:
The fault recovery problems was corrected in FPGA build versions x0346 and later. The rcvMiiBuffer will correctly clear itself after an overflow. The xmitMiiReg will release xmitHoldRcvBuf within 8 clocks after a fault, preventing an rcvMiiBuffer overflow. 8 clocks will guarantee that there is minimum packet spacing between the packets. sqPll will ignore the second SYNQ packet after fault recovery (in case packet delays were effected in the cycle where fault recovery occurred). The rcvMii will correctly handle a valid packet with data length of 0. No software changes are required.
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Problems with quadrature encoder feedback |
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Reference Number: FP 297 |
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Type: Bug Fix |
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FPGA Version: 0x0346 |
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Problem/Cause:
The pins for encA[0] & encB[0] were swapped, causing problems with quadrature encoder feedback. This problem existed for all FPGA versions prior to x0346. |
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Fix/Solution:
The FPGA design was modifed to correct the pinout. This problem was corrected in FPGA version x0346 and later.
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