Release Note
C0FE0035_xxxx.sff

Problem/Cause:
C0FE0035 pins gpio0_z[8:15] and gpio1_z[8:15] are not functional (only 8 GPIO pins per motor were instantiated). Also, primary quadrature feedback is instantiated for both motors (specification calls for no primary quadrature logic). These problems existed in all versions of C0FE0035 prior to x0343.

Fix/Solution:
FPGA code was corrected to instantiate 16 GPIO pins per motor, and remove primary feedback quadrature logic. This fix is included in versions x0343 and later. No software changes are required.

Description:
Add support for multiple packets to the rxMiiBuffer. This improves tolerance to network jitter. Prior to version x0341, the rxMiiBuffer could absorb up to 32 clocks (1.28 µS) of delay for a single packet, but only 8 clocks for multiple packets with minimum spacing. This change is required to meet theoretical worst-case network jitter in large networks (32 nodes). The improvement may also help at network startup, since the node's PLL phase error is larger than normal (as the PLL pulls into nominal lock). No software changes are required.

Description:
Add BranchRev register. This extends the existing 16 bits of FPGA version number with 8 bits of branch and 8 bits of revision ID.

Description:
Release new FPGA type C0FE0035_0340.sff.