Release Note
C0FE0030_xxxx.sff

Problem/Cause:
C0FE0030 SPI bus transmit data may be corrupted. The dual port buffer logic was running on 25 MHz clock instead of 50 MHz clock. This problem only exists in version x0341.

Problem/Cause:
FPGA code was corrected to use 50 MHz clock. This fix is in version x0342 and later. No software changes are required.

Description:
Add support for multiple packets to the rxMiiBuffer. This improves tolerance to network jitter. Prior to version x0341, the rxMiiBuffer could absorb up to 32 clocks (1.28 µS) of delay for a single packet, but only 8 clocks for multiple packets with minimum spacing. This change is required to meet theoretical worst-case network jitter in large networks (32 nodes). The improvement may also help at network startup, since the node's PLL phase error is larger than normal (as the PLL pulls into nominal lock). No software changes are required.

Problem/Cause:
The nodeIoSpi module does not work correctly when configured for a 12.5 MHz SPI bus clock rate.

Fix/Solution:
The FPGA code was modifed to use a 50 MHz clock rate in the nodeIoSpi module, allowing 12.5 MHz SPI bus clock rate in FPGA versions x0341 and later. No software changes are required.

Description:
Add BranchRev register. This extends the existing 16 bits of FPGA version number with 8 bits of branch and 8 bits of revision ID.